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M25PX64-STVMF6F Datasheet(PDF) 59 Page - Numonyx B.V

Part # M25PX64-STVMF6F
Description  64-Mbit, dual I/O, 4-Kbyte subsector erase, serial flash memory with 75 MHz SPI bus interface
PDF  66 Pages
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Manufacturer  NUMONYX [Numonyx B.V]
Direct Link  http://www.numonyx.com
Logo NUMONYX - Numonyx B.V

M25PX64-STVMF6F Datasheet(HTML) 59 Page - Numonyx B.V

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M25PX64
DC and AC parameters
59/66
Figure 30.
Serial input timing
tW
Write status register cycle time
1.3
15
ms
tPP
(8)
Page program cycle time (256 bytes)
0.8
5
ms
Page program cycle time (n bytes)
int(n/8) × 0.025(9)
Program OTP cycle time (64 bytes)
0.2
ms
tSSE
Subsector erase cycle time
70
150
ms
tSE
Sector erase cycle time
0.7
3
s
tBE
Bulk erase cycle time
68
160
s
Bulk erase cycle time (VPP = VPPH)35
1.
Preliminary data.
2.
Typical values given for TA = 25° C.
3.
tCH + tCL must be greater than or equal to 1/ fC.
4.
Value guaranteed by characterization, not 100% tested in production.
5.
Expressed as a slew-rate.
6.
Only applicable as a constraint for a WRSR instruction when SRWD is set to ‘1’.
7.
VPPH should be kept at a valid level until the program or erase operation has completed and its result
(success or failure) is known.
8.
When using the page program (PP) instruction to program consecutive bytes, optimized timings are
obtained with one sequence including all the bytes versus several sequences of only a few bytes (1
≤ n ≤
256).
9.
int(A) corresponds to the upper integer part of A. For example int(12/8) = 2, int(32/8) = 4 int(15.3) =16.
Table 17.
AC characteristics(1) (continued)
Test conditions specified in Table 13 and Table 14
Symbol
Alt.
Parameter
Min
Typ(2)
Max
Unit
C
DQ0
AI13728
S
MSB IN
DQ1
tDVCH
High Impedance
LSB IN
tSLCH
tCHDX
tCHCL
tCLCH
tSHCH
tSHSL
tCHSH
tCHSL



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