M25PX64-STVMF6F datasheet(26/66 Pages) NUMONYX

26 / 66 page

Instructions

M25PX64

26/66

Instructions

All instructions, addresses and data are shifted in and out of the device, most significant bit

first.

Serial data input(s) DQ0 (DQ1) is (are) sampled on the first rising edge of Serial Clock (C)

after Chip Select (S) is driven Low. Then, the one-byte instruction code must be shifted in to

the device, most significant bit first, on serial data input(s) DQ0 (DQ1), each bit being

latched on the rising edges of Serial Clock (C).

The instruction set is listed in Table 5.

Every instruction sequence starts with a one-byte instruction code. Depending on the

instruction, this might be followed by address bytes, or by data bytes, or by both or none.

In the case of a read data bytes (READ), read data bytes at higher speed (FAST_READ),

dual output fast read (DOFR), read OTP (ROTP), read lock registers (RDLR), read status

instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip

Select (S) can be driven High after any bit of the data-out sequence is being shifted out.

In the case of a page program (PP), program OTP (POTP), dual input fast program (DIFP),

subsector erase (SSE), sector erase (SE), bulk erase (BE), write status register (WRSR),

write to lock register (WRLR), write enable (WREN), write disable (WRDI) or deep power-

down (DP) instruction, Chip Select (S) must be driven High exactly at a byte boundary,

otherwise the instruction is rejected, and is not executed. That is, Chip Select (S) must

driven High when the number of clock pulses after Chip Select (S) being driven Low is an

exact multiple of eight.

All attempts to access the memory array during a write status register cycle, program cycle

or erase cycle are ignored, and the internal write status register cycle, program cycle or

erase cycle continues unaffected.

Note:

Output Hi-Z is defined as the point where data out is no longer driven.

M25PX64-STVMF6F Datasheet(PDF) 26 Page - Numonyx B.V