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PSD511B1 Datasheet(PDF) 109 Page - STMicroelectronics |
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PSD511B1 Datasheet(HTML) 109 Page - STMicroelectronics |
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109 / 153 page  PSD5XX Family 106 System Configuration (Cont.) Register Name Address Register Name Address Offset Offset PAGE REGISTER E1 INTR. READ CLEAR D5 INTR. MASK D2 INTR. EDGE/LEVEL D3 INTR. REQUEST D0 INTR. PRIORITY D1 LATCH STATUS VM C1 PMMR1 B0 PMMR0 B1 STATUS FLAGS A8 GLOBAL COMMAND A9 DLCY A7 SOFTWARE LOAD/STORE A4 FREEZE COMMAND A5 CMD3 A2 CMD2 A3 CMD1 A0 CMD0 A1 CNTR3 9E CNTR3 9F CNTR2 9C CNTR2 9D CNTR1 9A CNTR1 9B CNTR0 98 CNTR0 99 IMG3 96 IMG3 97 IMG2 94 IMG2 95 IMG1 92 IMG1 93 IMG0 90 IMG0 91 Table 31a. Other Register Address Offset (For 16-Bit Motorola MCUs in 16-Bit Mode. If 8-Bit Mode is selected, use Table 31.) Register Name Register Function Data In This Register is used to read the input on the port pins. Control A “0” sets the corresponding port pin in Address Out Mode. A “1” sets the pin in MCU I/O Mode. Data Out Holds the output data in the MCU I/O Mode. Direction This register is used to control the data flow in the I/O ports. A “0” sets the corresponding pin as an input pin. A “1” sets the pin as an output pin. Open Drain A “0” sets the corresponding pin driver as a CMOS driver. A “1” sets the pin driver as an Open Drain Driver. Special Function A “1” sets the corresponding port pin as Timer or Interrupt Output. PLD – I/O A read only status register; a “1” indicates the corresponding pin is configured as a PLD pin. Macrocell Out This register holds the outputs of the GPLD macrocells. Table 32. I/O Register Function |
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