PSD511B1 datasheet(127/153 Pages) STMICROELECTRONICS

127 / 153 page

NOTES: 1. Any input used to select an internal ZPSD5XX function.

2. In multiplexed mode latched address generated from ADIO delay to address output on any Port.

3. WR timing has the same timing as E, DS, LDS, UDS, WRL, WRH signals.

PSD5XX Family

124

-20

-25

EPROM_CMiser

Symbol

Parameter

Conditions

Min Max Min Max

Unit

tLVLX

ALE or AS Pulse Width

tAVLX

Address Setup Time

(Note 1)

tLXAX

Address Hold Time

(Note 1)

tAVWL

Address Valid to Leading

Edge of WR

(Notes 1 and 3)

t SLWL

CS Valid to Leading Edge of WR

(Note 3)

t DVWH

WR Data Setup Time

(Note 3)

t WHDX

WR Data Hold Time

(Note 3)

t WLWH

WR Pulse Width

(Note 3)

tWHAX

Trailing Edge of WR to Address

Invalid

(Note 3)

tWHPV

Trailing Edge of WR to Port

Output Valid

(Note 3)

In 16-Bit Data Bus

Address Input Valid to

Mode (Note 2)

tAVPV

Address Output Delay

In 8-Bit Data Bus

Mode (Note 2)

Write Timing (3.0 V ± 10%)

Microcontroller Interface – AC/DC Parameters

(ZPSD5XXV Versions)

PSD511B1 Datasheet(PDF) 127 Page - STMicroelectronics

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