T89C51AC2-RLSI-M datasheet(61/117 Pages) ATMEL

61 / 117 page

Draft.A - March 30, 2001

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T89C51AC2

12.6. Registers

TCON (S:88h)

Timer/Counter Control Register.

Reset Value= 0000 0000b

Figure 47. TCON Register

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

Bit Number Bit Mnemonic

Description

TF1

Timer 1 Overflow Flag

Cleared by hardware when processor vectors to interrupt routine.

Set by hardware on Timer/Counter overflow, when Timer 1 register overflows.

TR1

Timer 1 Run Control Bit

Clear to turn off Timer/Counter 1.

Set to turn on Timer/Counter 1.

TF0

Timer 0 Overflow Flag

Cleared by hardware when processor vectors to interrupt routine.

Set by hardware on Timer/Counter overflow, when Timer 0 register overflows.

TR0

Timer 0 Run Control Bit

Clear to turn off Timer/Counter 0.

Set to turn on Timer/Counter 0.

IE1

Interrupt 1 Edge Flag

Cleared by hardware when interrupt is processed if edge-triggered (see IT1).

Set by hardware when external interrupt is detected on INT1# pin.

IT1

Interrupt 1 Type Control Bit

Clear to select low level active (level triggered) for external interrupt 1 (INT1#).

Set to select falling edge active (edge triggered) for external interrupt 1.

IE0

Interrupt 0 Edge Flag

Cleared by hardware when interrupt is processed if edge-triggered (see IT0).

Set by hardware when external interrupt is detected on INT0# pin.

IT0

Interrupt 0 Type Control Bit

Clear to select low level active (level triggered) for external interrupt 0 (INT0#).

Set to select falling edge active (edge triggered) for external interrupt 0.

T89C51AC2-RLSI-M Datasheet(PDF) 61 Page - ATMEL Corporation

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