T89C51AC2-RLSI-M datasheet(20/117 Pages) ATMEL

20 / 117 page

Draft.A - March 30, 2001

Preview - Confidential

T89C51AC2

7.3. FLASH Memory Architecture

T89C51AC2 features two on-chip flash memories:

• Flash memory FM0:

containing 32 Kbytes of program memory (user space) organized into 128 byte pages,

• Flash memory FM1:

2 Kbytes for boot loader and Application Programming Interfaces (API).

The FM0 supports both parallel programming and Serial In-System Programming (ISP) whereas FM1 supports

only parallel programming by programmers. The ISP mode is detailed in the "In-System Programming" section.

All Read/Write access operations on FLASH Memory by user application are managed by a set of API described

in the "In-System Programming" section.

Figure 11. Flash memory architecture

7.3.1. FM0 Memory Architecture

The flash memory is made up of 4 blocks (see Figure 11):

1. The memory array (user space) 32 Kbytes

2. The Extra Row

3. The Hardware security bits

4. The column latch registers

7.3.1.1. User Space

This space is composed of a 32 Kbytes FLASH memory organized in 256 pages of 128 bytes. It contains the

user’s application code.

7.3.1.2. Extra Row (XRow)

This row is a part of FM0 and has a size of 128 bytes. The extra row may contain information for boot loader usage.

7FFFh

32 Kbytes

Flash memory

FM0

0000h

Hardware Security (1 byte)

Column Latches (128 bytes)

user space

Extra Row (128 bytes)

2 Kbytes

Flash memory

FM1

boot space

FFFFh

F800h

FM1 mapped between FFFFh and

F800h when bit ENBOOT is set in

AUXR1 register

T89C51AC2-RLSI-M Datasheet(PDF) 20 Page - ATMEL Corporation

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