T89C51AC2-RLSI-M datasheet(82/117 Pages) ATMEL

82 / 117 page

Draft.A - March 30, 2001

Preview - Confidential

T89C51AC2

15.8. PCA Registers

CMOD (S:D8h)

PCA Counter Mode Register

Reset Value = 00XX X000b

Figure 70. CMOD Register

CIDL

WDTE

CPS1

CPS0

ECF

Bit Number Bit Mnemonic

Description

CIDL

PCA Counter Idle Control bit

Clear to let the PCA run during Idle mode.

Set to stop the PCA when Idle mode is invoked.

WDTE

Watchdog Timer Enable

Clear to disable Watchdog Timer function on PCA Module 4,

Set to enable it.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

CPS1

EWC Count Pulse Select bits

CPS1

CPS0

Clock source

Internal Clock, FPca/6

Internal Clock, FPca/2

Timer 0 overflow

External clock at ECI/P1.2 pin (Max. Rate = FPca/4)

CPS0

ECF

Enable PCA Counter Overflow Interrupt bit

Clear to disable CF bit in CCON register to generate an interrupt.

Set to enable CF bit in CCON register to generate an interrupt.

T89C51AC2-RLSI-M Datasheet(PDF) 82 Page - ATMEL Corporation

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