T89C51AC2-RLSI-M datasheet(54/117 Pages) ATMEL

54 / 117 page

Draft.A - March 30, 2001

Preview - Confidential

T89C51AC2

11.5. REGISTERS

SCON (S:98h)

Serial Control Register

Reset Value = 0000 0000b

Bit addressable

Figure 37. SCON Register

FE/SM0

SM1

SM2

REN

TB8

RB8

Bit Number Bit Mnemonic

Description

7FE

Framing Error bit (SMOD0=1)

Clear to reset the error state, not cleared by a valid stop bit.

Set by hardware when an invalid stop bit is detected.

SM0

Serial port Mode bit 0 (SMOD0=0)

Refer to SM1 for serial port mode selection.

SM1

Serial port Mode bit 1

SM0

SM1

ModeBaud Rate

Shift RegisterFXTAL/12

8-bit UARTVariable

9-bit UARTFXTAL/64 or FXTAL/32

9-bit UARTVariable

SM2

Serial port Mode 2 bit / Multiprocessor Communication Enable bit

Clear to disable multiprocessor communication feature.

Set to enable multiprocessor communication feature in mode 2 and 3.

REN

Reception Enable bit

Clear to disable serial reception.

Set to enable serial reception.

TB8

Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3

Clear to transmit a logic 0 in the 9th bit.

Set to transmit a logic 1 in the 9th bit.

RB8

Receiver Bit 8 / Ninth bit received in modes 2 and 3

Cleared by hardware if 9th bit received is a logic 0.

Set by hardware if 9th bit received is a logic 1.

1TI

Transmit Interrupt flag

Clear to acknowledge interrupt.

Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other

modes.

0RI

Receive Interrupt flag

Clear to acknowledge interrupt.

Set by hardware at the end of the 8th bit time in mode 0, see Figure 35. and Figure 36. in the other modes.

T89C51AC2-RLSI-M Datasheet(PDF) 54 Page - ATMEL Corporation

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