T89C51AC2-RLSI-M datasheet(60/117 Pages) ATMEL

60 / 117 page

Draft.A - March 30, 2001

Preview - Confidential

T89C51AC2

12.4.2. Mode 1 (16-bit Timer)

Mode 1 configures Timer 1 as a 16-bit Timer with TH1 and TL1 registers connected in cascade (see Figure 43).

The selected input increments TL1 register.

12.4.3. Mode 2 (8-bit Timer with Auto-Reload)

Mode 2 configures Timer 1 as an 8-bit Timer (TL1 register) with automatic reload from TH1 register on overflow

(see Figure 44). TL1 overflow sets TF1 flag in TCON register and reloads TL1 with the contents of TH1, which

is preset by software. The reload leaves TH1 unchanged.

12.4.4. Mode 3 (Halt)

Placing Timer 1 in mode 3 causes it to halt and hold its count. This can be used to halt Timer 1 when TR1 run

control bit is not available i.e. when Timer 0 is in mode 3.

12.5. Interrupt

Each Timer handles one interrupt source that is the timer overflow flag TF0 or TF1. This flag is set every time

an overflow occurs. Flags are cleared when vectoring to the Timer interrupt routine. Interrupts are enabled by

setting ETx bit in IEN0 register. This assumes interrupts are globally enabled by setting EA bit in IEN0 register.

Figure 46. Timer Interrupt System

TF0

TCON.5

ET0

IEN0.1

Timer 0

Interrupt Request

TF1

TCON.7

ET1

IEN0.3

Timer 1

Interrupt Request

T89C51AC2-RLSI-M Datasheet(PDF) 60 Page - ATMEL Corporation