H8SLASH3008 datasheet(95/686 Pages) RENESAS

95 / 686 page

2. CPU

Rev.4.00 Aug. 20, 2007 Page 51 of 638

REJ09B0395-0400

The reset state can also be entered by a watchdog timer overflow. For details see section 11,

Watchdog Timer.

2.8.7

Power-Down State

In the power-down state the CPU stops operating to conserve power. There are three modes: sleep

mode, software standby mode, and hardware standby mode.

Sleep Mode: A transition to sleep mode is made if the SLEEP instruction is executed while the

SSBY bit is cleared to 0 in the system control register (SYSCR). CPU operations stop

immediately after execution of the SLEEP instruction, but the contents of CPU registers are

retained.

Software Standby Mode: A transition to software standby mode is made if the SLEEP

instruction is executed while the SSBY bit is set to 1 in SYSCR. The CPU and clock halt and all

on-chip supporting modules stop operating. The on-chip supporting modules are reset, but as long

as a specified voltage is supplied the contents of CPU registers and on-chip RAM are retained.

The I/O ports also remain in their existing states.

Hardware Standby Mode: A transition to hardware standby mode is made when the

STBY input

goes low. As in software standby mode, the CPU and all clocks halt and the on-chip supporting

modules are reset, but as long as a specified voltage is supplied, on-chip RAM contents are

retained.

For further information see section 18, Power-Down State.

2.9

Basic Operational Timing

2.9.1

Overview

The H8/300H CPU operates according to the system clock (

φ). The interval from one rise of the

system clock to the next rise is referred to as a “state.” A memory cycle or bus cycle consists of

two or three states. The CPU uses different methods to access on-chip memory, the on-chip

supporting modules, and the external address space. Access to the external address space can be

controlled by the bus controller.

2.9.2

On-Chip Memory Access Timing

On-chip memory is accessed in two states. The data bus is 16 bits wide, permitting both byte and

word access. Figure 2.15 shows the on-chip memory access cycle. Figure 2.16 indicates the pin

states. The H8/3008 has a function for changing the method of outputting addresses from the

address pins. For details see section 6.3.5, Address Output Method.

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