H8SLASH3008 datasheet(23/686 Pages) RENESAS

23 / 686 page

Rev.4.00 Aug. 20, 2007, Page xxiii of xliv

REJ09B0395-0400

10.2

Register Descriptions ........................................................................................................ 287

10.2.1 Port A Data Direction Register (PADDR) ........................................................... 287

10.2.2 Port A Data Register (PADR) .............................................................................. 287

10.2.3 Port B Data Direction Register (PBDDR)............................................................ 288

10.2.4 Port B Data Register (PBDR) .............................................................................. 288

10.2.5 Next Data Register A (NDRA) ............................................................................ 289

10.2.6 Next Data Register B (NDRB)............................................................................. 291

10.2.7 Next Data Enable Register A (NDERA).............................................................. 293

10.2.8 Next Data Enable Register B (NDERB) .............................................................. 294

10.2.9 TPC Output Control Register (TPCR) ................................................................. 295

10.2.10 TPC Output Mode Register (TPMR) ................................................................... 298

10.3

Operation........................................................................................................................... 300

10.3.1 Overview.............................................................................................................. 300

10.3.2 Output Timing...................................................................................................... 301

10.3.3 Normal TPC Output ............................................................................................. 302

10.3.4 Non-Overlapping TPC Output ............................................................................. 304

10.3.5 TPC Output Triggering by Input Capture ............................................................ 306

10.4

Usage Notes ...................................................................................................................... 307

10.4.1 Operation of TPC Output Pins ............................................................................. 307

10.4.2 Note on Non-Overlapping Output........................................................................ 307

Section 11 Watchdog Timer............................................................................................. 309

11.1

Overview........................................................................................................................... 309

11.1.1 Features ................................................................................................................ 309

11.1.2 Block Diagram ..................................................................................................... 310

11.1.3 Pin Configuration................................................................................................. 310

11.1.4 Register Configuration......................................................................................... 311

11.2

Register Descriptions ........................................................................................................ 311

11.2.1 Timer Counter (TCNT)........................................................................................ 311

11.2.2 Timer Control/Status Register (TCSR) ................................................................ 312

11.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 314

11.2.4 Notes on Register Access..................................................................................... 315

11.3

Operation........................................................................................................................... 317

11.3.1 Watchdog Timer Operation ................................................................................. 317

11.3.2 Interval Timer Operation ..................................................................................... 318

11.3.3 Timing of Setting of Overflow Flag (OVF) ......................................................... 318

11.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) .................................. 319

11.4

Interrupts ........................................................................................................................... 320

11.5

Usage Notes ...................................................................................................................... 320

H8/3008 Datasheet(PDF) 23 Page - Renesas Technology Corp

H8/3008 Datasheet(HTML) 23 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL