H8SLASH3008 datasheet(29/686 Pages) RENESAS

29 / 686 page

Rev.4.00 Aug. 20, 2007, Page xxix of xliv

REJ09B0395-0400

Figures

Section 1 Overview

Figure 1.1

Block Diagram ...................................................................................................

Figure 1.2

Pin Arrangement of H8/3008 (FP-100B or TFP-100B Package, Top View) .....

Section 2 CPU

Figure 2.1

CPU Operating Modes ....................................................................................... 18

Figure 2.2

Memory Map...................................................................................................... 19

Figure 2.3

CPU Registers .................................................................................................... 20

Figure 2.4

Usage of General Registers ................................................................................ 21

Figure 2.5

Stack ................................................................................................................... 22

Figure 2.6

General Register Data Formats (1) ..................................................................... 24

Figure 2.7

General Register Data Formats (2) ..................................................................... 25

Figure 2.8

Memory Data Formats........................................................................................ 26

Figure 2.9

Instruction Formats............................................................................................. 39

Figure 2.10

Memory-Indirect Branch Address Specification ................................................ 43

Figure 2.11

Processing States ................................................................................................ 47

Figure 2.12

Classification of Exception Sources ................................................................... 48

Figure 2.13

State Transitions ................................................................................................. 49

Figure 2.14

Stack Structure after Exception Handling .......................................................... 50

Figure 2.15

On-Chip Memory Access Cycle......................................................................... 52

Figure 2.16

Pin States during On-Chip Memory Access (Address Update Mode 1)............. 52

Figure 2.17

Access Cycle for On-Chip Supporting Modules ................................................ 53

Figure 2.18

Pin States during Access to On-Chip Supporting Modules ................................ 53

Section 3 MCU Operating Modes

Figure 3.1

Memory Map of H8/3008 in Each Operating Mode........................................... 63

Section 4 Exception Handling

Figure 4.1

Exception Sources .............................................................................................. 66

Figure 4.2

Reset Sequence (Modes 1 and 3)........................................................................ 69

Figure 4.3

Reset Sequence (Modes 2 and 4)........................................................................ 70

Figure 4.4

Interrupt Sources and Number of Interrupts ....................................................... 71

Figure 4.5

Stack after Completion of Exception Handling.................................................. 72

Figure 4.6

Operation when SP Value is Odd ....................................................................... 74

Section 5 Interrupt Controller

Figure 5.1

Interrupt Controller Block Diagram ................................................................... 76

Figure 5.2

Block Diagram of Interrupts IRQ

5 to IRQ0 .........................................................

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