H8SLASH3008 datasheet(19/686 Pages) RENESAS

19 / 686 page

Rev.4.00 Aug. 20, 2007, Page xix of xliv

REJ09B0395-0400

5.1.2

Block Diagram ..................................................................................................... 76

5.1.3

Pin Configuration................................................................................................. 77

5.1.4

5.2

Register Descriptions ........................................................................................................ 78

5.2.1

System Control Register (SYSCR) ...................................................................... 78

5.2.2

Interrupt Priority Registers A and B (IPRA, IPRB) ............................................. 79

5.2.3

IRQ Status Register (ISR).................................................................................... 84

5.2.4

IRQ Enable Register (IER) .................................................................................. 85

5.2.5

IRQ Sense Control Register (ISCR) .................................................................... 86

5.3

Interrupt Sources ............................................................................................................... 87

5.3.1

External Interrupts ............................................................................................... 87

5.3.2

Internal Interrupts................................................................................................. 88

5.3.3

Interrupt Exception Handling Vector Table......................................................... 88

5.4

Interrupt Operation............................................................................................................ 92

5.4.1

Interrupt Handling Process................................................................................... 92

5.4.2

Interrupt Exception Handling Sequence .............................................................. 97

5.4.3

Interrupt Response Time...................................................................................... 98

5.5

Usage Notes ...................................................................................................................... 99

5.5.1

Contention between Interrupt and Interrupt-Disabling Instruction ...................... 99

5.5.2

Instructions that Inhibit Interrupts........................................................................ 100

5.5.3

Interrupts during EEPMOV Instruction Execution .............................................. 100

Section 6 Bus Controller.................................................................................................... 101

6.1

Overview........................................................................................................................... 101

6.1.1

Features ................................................................................................................ 101

6.1.2

Block Diagram ..................................................................................................... 102

6.1.3

Pin Configuration................................................................................................. 103

6.1.4

6.2

Register Descriptions ........................................................................................................ 104

6.2.1

Bus Width Control Register (ABWCR)............................................................... 104

6.2.2

Access State Control Register (ASTCR) ............................................................. 105

6.2.3

Wait Control Registers H and L (WCRH, WCRL).............................................. 106

6.2.4

Bus Release Control Register (BRCR) ................................................................ 110

6.2.5

Bus Control Register (BCR) ................................................................................ 111

6.2.6

Chip Select Control Register (CSCR).................................................................. 114

6.2.7

Address Control Register (ADRCR).................................................................... 115

6.3

Operation........................................................................................................................... 116

6.3.1

Area Division ....................................................................................................... 116

6.3.2

Bus Specifications................................................................................................ 118

6.3.3

Memory Interfaces ............................................................................................... 119

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