H8SLASH3008 datasheet(10/686 Pages) RENESAS

10 / 686 page

Rev.4.00 Aug. 20, 2007 page x of xliv

REJ09B0395-0400

Item

Page

Revision (See Manual for Details)

9.4.5 Operation with

Cascaded Connection

Compare Match Count

Mode

267

Description amended

• Channels 0 and 1:

When bits CKS2 to CKS0 are set to (100) in 8TCR1,

8TCNT1 counts channel 0 compare match A events.

Channels 0 and 1 are controlled independently.

CMF flag setting, interrupt generation, TMO pin output,

counter clearing, and so on, is in accordance with the

settings for each channel.

Note: When bit ICE = 1 in 8TCSR1, the compare match

used.

• Channels 2 and 3:

When bits CKS2 to CKS0 are set to (100) in 8TCR3,

8TCNT3 counts channel 2 compare match A events.

Channels 2 and 3 are controlled independently.

CMF flag setting, interrupt generation, TMO pin output,

counter clearing, and so on, is in accordance with the

settings for each channel.

Note: When bit ICE = 1 in 8TCSR3, the compare match

used.

9.7.1 Contention

between 8TCNT Write

and Clear

Figure 9.18 Contention

between 8TCNT Write

and Clear

272

Figure amended

Address bus

8TCNT address

Internal write signal

Counter clear signal

8TCNT

H'00

8TCNT write cycle

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