H8SLASH3024F datasheet(33/841 Pages) RENESAS

33 / 841 page

Rev. 2.00 Sep 20, 2005 page xxxiii of xxxviii

Tables

Section 1 Overview

Table 1.1

Features................................................................................................................

Table 1.2

Comparison of H8/3024 Group Pin Arrangements..............................................

Table 1.3

Pin Functions .......................................................................................................

Table 1.4

Pin Assignments in Each Mode (FP-100B or TFP-100B, FP-100A) ..................

Section 2 CPU

Table 2.1

Instruction Classification .....................................................................................

Table 2.2

Instructions and Addressing Modes.....................................................................

Table 2.3

Data Transfer Instructions ...................................................................................

Table 2.4

Arithmetic Operation Instructions .......................................................................

Table 2.5

Logic Operation Instructions ...............................................................................

Table 2.6

Shift Instructions..................................................................................................

Table 2.7

Bit Manipulation Instructions ..............................................................................

Table 2.8

Branching Instructions.........................................................................................

Table 2.9

System Control Instructions.................................................................................

Table 2.10

Block Transfer Instruction ...................................................................................

Table 2.11

Addressing Modes ...............................................................................................

Table 2.12

Absolute Address Access Ranges........................................................................

Table 2.13

Effective Address Calculation .............................................................................

Table 2.14

Exception Handling Types and Priority...............................................................

Section 3 MCU Operating Modes

Table 3.1

Operating Mode Selection ...................................................................................

Table 3.2

Registers ..............................................................................................................58

Table 3.3

Pin Functions in Each Mode................................................................................

Table 3.4

Address Maps in Mode 5.....................................................................................

Section 4 Exception Handling

Table 4.1

Exception Types and Priority ..............................................................................

Table 4.2

Exception Vector Table .......................................................................................

Section 5 Interrupt Controller

Table 5.1

Interrupt Pins .......................................................................................................

Table 5.2

Interrupt Controller Registers ..............................................................................

Table 5.3

Interrupt Sources, Vector Addresses, and Priority...............................................

Table 5.4

UE, I, and UI Bit Settings and Interrupt Handling............................................... 100

Table 5.5

Interrupt Response Time...................................................................................... 106

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