H8SLASH3024F datasheet(40/841 Pages) RENESAS

40 / 841 page

Section 1 Overview

Rev. 2.00 Sep 20, 2005 page 2 of 800

REJ09B0260-0200

Table 1.1

Features

Feature

Description

CPU

Upward-compatible with the H8/300 CPU at the object-code level

General-register machine

• Sixteen 16-bit general registers

(also usable as sixteen 8-bit registers plus eight 16-bit registers, or as eight

32-bit registers)

High-speed operation

Maximum

clock rate

Add/

subtract

Multiply/

divide

H8/3024F-ZTAT

H8/3026F-ZTAT

H8/3024 (mask ROM version)

H8/3026 (mask ROM version)

25 MHz

80 ns

560 ns

16-Mbyte address space

Instruction features

• 8/16/32-bit data transfer, arithmetic, and logic instructions

• Signed and unsigned multiply instructions (8 bits × 8 bits, 16 bits × 16 bits)

• Signed and unsigned divide instructions (16 bits ÷ 8 bits, 32 bits ÷ 16 bits)

• Bit accumulator function

Bit manipulation instructions with register-indirect specification of bit positions

Memory

ROM

RAM

H8/3024F-ZTAT

H8/3024 (mask ROM version)

128 kbytes

4 kbytes

H8/3026F-ZTAT

H8/3026 (mask ROM version)

256 kbytes

8 kbytes

Interrupt

controller

• Seven external interrupt pins: NMI, IRQ0 to IRQ5

• 27 internal interrupts

• Three selectable interrupt priority levels

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