H8SLASH3024F datasheet(15/841 Pages) RENESAS

15 / 841 page

Rev. 2.00 Sep 20, 2005 page xv of xxxviii

9.7.7

Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode

(Cascaded Connection) ........................................................................................ 306

9.7.8

Contention between Compare Matches A and B ................................................. 307

9.7.9

8TCNT Operation and Internal Clock Source Switchover .................................. 307

Section 10 Programmable Timing Pattern Controller (TPC) ................................. 311

10.1

Overview........................................................................................................................... 311

10.1.1 Features................................................................................................................ 311

10.1.2 Block Diagram..................................................................................................... 312

10.1.3 Pin Configuration ................................................................................................ 313

10.1.4 Register Configuration......................................................................................... 314

10.2

Register Descriptions........................................................................................................ 315

10.2.1 Port A Data Direction Register (PADDR) ........................................................... 315

10.2.2 Port A Data Register (PADR).............................................................................. 315

10.2.3 Port B Data Direction Register (PBDDR) ........................................................... 316

10.2.4 Port B Data Register (PBDR) .............................................................................. 316

10.2.5 Next Data Register A (NDRA) ............................................................................ 317

10.2.6 Next Data Register B (NDRB) ............................................................................ 319

10.2.7 Next Data Enable Register A (NDERA).............................................................. 321

10.2.8 Next Data Enable Register B (NDERB) .............................................................. 322

10.2.9 TPC Output Control Register (TPCR) ................................................................. 323

10.2.10 TPC Output Mode Register (TPMR)................................................................... 326

10.3

Operation .......................................................................................................................... 328

10.3.1 Overview.............................................................................................................. 328

10.3.2 Output Timing ..................................................................................................... 329

10.3.3 Normal TPC Output............................................................................................. 330

10.3.4 Non-Overlapping TPC Output............................................................................. 332

10.3.5 TPC Output Triggering by Input Capture ............................................................ 334

10.4

Usage Notes ...................................................................................................................... 335

10.4.1 Operation of TPC Output Pins............................................................................. 335

10.4.2 Note on Non-Overlapping Output ....................................................................... 335

Section 11 Watchdog Timer............................................................................................. 337

11.1

Overview........................................................................................................................... 337

11.1.1 Features................................................................................................................ 337

11.1.2 Block Diagram..................................................................................................... 338

11.1.3 Pin Configuration ................................................................................................ 338

11.1.4 Register Configuration......................................................................................... 339

11.2

Register Descriptions........................................................................................................ 339

11.2.1 Timer Counter (TCNT)........................................................................................ 339

11.2.2 Timer Control/Status Register (TCSR)................................................................ 340

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