H8SLASH3024F datasheet(90/841 Pages) RENESAS

90 / 841 page

Section 2 CPU

Rev. 2.00 Sep 20, 2005 page 52 of 800

REJ09B0260-0200

is cleared to 0, the CPU sets both the I bit and the UI bit in the condition code register to 1. Then

the CPU fetches a start address from the exception vector table and execution branches to that

address.

Figure 2.14 shows the stack after the exception-handling sequence.

SP–4

SP–3

SP–2

SP–1

SP (ER7)

Before exception

handling starts

SP (ER7)

SP+1

SP+2

SP+3

SP+4

After exception

handling ends

Stack area

CCR

Even

address

Pushed on stack

Legend:

CCR:

SP:

Condition code register

Stack pointer

Notes: 1.

PC is the address of the first instruction executed after the return from the

exception-handling routine.

Registers must be saved and restored by word access or longword access,

starting at an even address.

Figure 2.14 Stack Structure after Exception Handling

2.8.5

Bus-Released State

In this state the bus is released to a bus master other than the CPU, in response to a bus request.

The bus masters other than the CPU is an external bus master. While the bus is released, the CPU

halts except for internal operations. Interrupt requests are not accepted. For details see section 6.6,

Bus Arbiter.

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