H8SLASH3024F datasheet(41/841 Pages) RENESAS

41 / 841 page

Section 1 Overview

Rev. 2.00 Sep 20, 2005 page 3 of 800

REJ09B0260-0200

Feature

Description

Bus controller

• Address space can be partitioned into eight areas, with independent bus

specifications in each area

• Chip select output available for areas 0 to 7

• 8-bit access or 16-bit access selectable for each area

• Two-state or three-state access selectable for each area

• Selection of two wait modes

• Number of program wait states selectable for each area

• Bus arbitration function

• Two address update modes

16-bit timer,

3 channels

• Three 16-bit timer channels, capable of processing up to six pulse outputs or

six pulse inputs

• 16-bit timer counter (channels 0 to 2)

• Two multiplexed output compare/input capture pins (channels 0 to 2)

• Operation can be synchronized (channels 0 to 2)

• PWM mode available (channels 0 to 2)

• Phase counting mode available (channel 2)

8-bit timer,

4 channels

• 8-bit up-counter (external event count capability)

• Two time constant registers

• Two channels can be connected

Programmable

timing pattern

controller (TPC)

• Maximum 16-bit pulse output, using 16-bit timer as time base

• Up to four 4-bit pulse output groups (or one 16-bit group, or two 8-bit groups)

• Non-overlap mode available

Watchdog

timer (WDT),

1 channel

• Internal reset signal can be generated by overflow

• Reset signal can be output externally (not available in on-chip flash memory

versions)

• Usable as an interval timer

Serial

communication

interface (SCI),

2 channels

• Selection of asynchronous or synchronous mode

• Full duplex: can transmit and receive simultaneously

• On-chip baud-rate generator

• Smart card interface functions added

H8/3024F Datasheet(PDF) 41 Page - Renesas Technology Corp

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