H8SLASH3024F datasheet(25/841 Pages) RENESAS

25 / 841 page

Rev. 2.00 Sep 20, 2005 page xxv of xxxviii

Figure 6.15

Bus Control Signal Timing for 16-Bit, Two-State-Access Area (3)

(Word Access) ..................................................................................................... 141

Figure 6.16

Example of Wait State Insertion Timing ............................................................. 142

Figure 6.17

Example of Idle Cycle Operation (ICIS1 = 1) ..................................................... 143

Figure 6.18

Example of Idle Cycle Operation (ICIS0 = 1) ..................................................... 144

Figure 6.19

Example of Idle Cycle Operation ........................................................................ 145

Figure 6.20

Example of External Bus Master Operation ........................................................ 148

Figure 6.21

ASTCR Write Timing.......................................................................................... 149

Figure 6.22

DDR Write Timing .............................................................................................. 149

Figure 6.23

BRCR Write Timing............................................................................................ 150

Section 7 I/O Ports

Figure 7.1

Port 1 Pin Configuration...................................................................................... 155

Figure 7.2

Port 2 Pin Configuration...................................................................................... 158

Figure 7.3

Port 3 Pin Configuration...................................................................................... 162

Figure 7.4

Port 4 Pin Configuration...................................................................................... 164

Figure 7.5

Port 5 Pin Configuration...................................................................................... 167

Figure 7.6

Port 6 Pin Configuration...................................................................................... 171

Figure 7.7

Port 7 Pin Configuration...................................................................................... 175

Figure 7.8

Port 8 Pin Configuration...................................................................................... 177

Figure 7.9

Port 9 Pin Configuration...................................................................................... 182

Figure 7.10

Port A Pin Configuration ..................................................................................... 188

Figure 7.11

Port B Pin Configuration ..................................................................................... 200

Section 8 16-Bit Timer

Figure 8.1

16-bit timer Block Diagram (Overall) ................................................................. 209

Figure 8.2

Block Diagram of Channels 0 and 1 .................................................................... 210

Figure 8.3

Block Diagram of Channel 2 ............................................................................... 211

Figure 8.4

16TCNT Access Operation [CPU

→ 16TCNT (Word)] ..................................... 235

Figure 8.5

Access to Timer Counter (CPU Reads 16TCNT, Word) ..................................... 235

Figure 8.6

Access to Timer Counter H (CPU Writes to 16TCNTH, Upper Byte)................ 236

Figure 8.7

Access to Timer Counter L (CPU Writes to 16TCNTL, Lower Byte) ................ 236

Figure 8.8

Access to Timer Counter H (CPU Reads 16TCNTH, Upper Byte)..................... 236

Figure 8.9

Access to Timer Counter L (CPU Reads 16TCNTL, Lower Byte) ..................... 237

Figure 8.10

16TCR Access (CPU Writes to 16TCR) ............................................................. 237

Figure 8.11

16TCR Access (CPU Reads 16TCR) .................................................................. 238

Figure 8.12

Counter Setup Procedure (Example) ................................................................... 239

Figure 8.13

Free-Running Counter Operation ........................................................................ 240

Figure 8.14

Periodic Counter Operation ................................................................................. 241

Figure 8.15

Count Timing for Internal Clock Sources............................................................ 241

Figure 8.16

Count Timing for External Clock Sources (when Both Edges are Detected) ...... 242

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