H8SLASH3024F datasheet(67/841 Pages) RENESAS

Part #	H8/3024F

Description	Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

PDF	841 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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67 / 841 page

Section 2 CPU

Rev. 2.00 Sep 20, 2005 page 29 of 800

REJ09B0260-0200

2.6

Instruction Set

2.6.1

Instruction Set Overview

The H8/300H CPU has 64 types of instructions, which are classified in table 2.1.

Table 2.1

Instruction Classification

Function

Instruction

Types

Data transfer

MOV, PUSH*

1, POP*1, MOVTPE*2, MOVFPE*2

Arithmetic operations

ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS,

MULXU, MULXS, DIVXU, DIVXS, CMP, NEG, EXTS, EXTU

Logic operations

AND, OR, XOR, NOT

Shift operations

SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR

Bit manipulation

BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR,

BIXOR, BLD, BILD, BST, BIST

Branch

Bcc*

3, JMP, BSR, JSR, RTS

System control

TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP

Block data transfer

EEPMOV

Total 64 types

Notes: 1. POP.W Rn is identical to MOV.W @SP+, Rn.

PUSH.W Rn is identical to MOV.W Rn, @–SP.

POP.L ERn is identical to MOV.L @SP+, Rn.

PUSH.L ERn is identical to MOV.L Rn, @–SP.

2. Not available in the H8/3024 Group.

3. Bcc is a generic branching instruction.

H8/3024F Datasheet(PDF) 67 Page - Renesas Technology Corp