H8SLASH3024F datasheet(83/841 Pages) RENESAS

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Section 2 CPU

Rev. 2.00 Sep 20, 2005 page 45 of 800

REJ09B0260-0200

7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and

BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is sign-

extended to 24 bits and added to the 24-bit PC contents to generate a 24-bit branch address. The

PC value to which the displacement is added is the address of the first byte of the next instruction,

so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to

+32768 bytes (–16383 to +16384 words) from the branch instruction. The resulting value should

be an even number.

8 Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The

instruction code contains an 8-bit absolute address specifying a memory operand. This memory

operand contains a branch address. The memory operand is accessed by longword access. The first

byte of the memory operand is ignored, generating a 24-bit branch address. See figure 2.10. The

upper bits of the 8-bit absolute address are assumed to be 0 (H'0000), so the address range is 0 to

255 (H'000000 to H'0000FF). Note that the first part of this range is also the exception vector area.

For further details see section 5, Interrupt Controller.

Specified by @aa:8

Reserved

Branch address

Figure 2.10 Memory-Indirect Branch Address Specification

When a word-size or longword-size memory operand is specified, or when a branch address is

specified, if the specified memory address is odd, the least significant bit is regarded as 0. The

accessed data or instruction code therefore begins at the preceding address. See section 2.5.2,

Memory Data Formats.

2.7.2

Effective Address Calculation

Table 2.13 explains how an effective address is calculated in each addressing mode. In the

1-Mbyte operating modes the upper 4 bits of the calculated address are ignored in order to

generate a 20-bit effective address.

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