MC9S08DN60F1CLF datasheet(138/356 Pages) FREESCALE

138 / 356 page

Chapter 8 Multi-Purpose Clock Generator (S08MCGV1)

MC9S08DN60 Series Data Sheet, Rev 3

138

Freescale Semiconductor

8.3.5

MCG Control Register 3 (MCGC3)

OSCINIT

OSC Initialization — If the external reference clock is selected by ERCLKEN or by the MCG being in FEE, FBE,

PEE, PBE, or BLPE mode, and if EREFS is set, then this bit is set after the initialization cycles of the external

oscillator clock have completed. This bit is only cleared when either EREFS is cleared or when the MCG is in

either FEI, FBI, or BLPI mode and ERCLKEN is cleared.

FTRIM

MCG Fine Trim — Controls the smallest adjustment of the internal reference clock frequency. Setting FTRIM

will increase the period and clearing FTRIM will decrease the period by the smallest amount possible.

If an FTRIM value stored in nonvolatile memory is to be used, it’s the user’s responsibility to copy that value from

the nonvolatile memory location to this register’s FTRIM bit.

654

210

LOLIE

PLLS

CME

VDIV

Reset:

Figure 8-7. MCG PLL Register (MCGPLL)

Table 8-5. MCG PLL Register Field Descriptions

Field

Description

LOLIE

Loss of Lock Interrupt Enable — Determines if an interrupt request is made following a loss of lock indication.

The LOLIE bit only has an effect when LOLS is set.

0 No request on loss of lock.

1 Generate an interrupt request on loss of lock.

PLLS

PLL Select — Controls whether the PLL or FLL is selected. If the PLLS bit is clear, the PLL is disabled in all

modes. If the PLLS is set, the FLL is disabled in all modes.

1 PLL is selected

0 FLL is selected

Table 8-4. MCG Status and Control Register Field Descriptions (continued)

Field

Description

MC9S08DN60F1CLF Datasheet(PDF) 138 Page - Freescale Semiconductor, Inc