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MC9S08DN60F1CLF Datasheet(PDF) 140 Page - Freescale Semiconductor, Inc |
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MC9S08DN60F1CLF Datasheet(HTML) 140 Page - Freescale Semiconductor, Inc |
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140 / 356 page  Chapter 8 Multi-Purpose Clock Generator (S08MCGV1) MC9S08DN60 Series Data Sheet, Rev 3 140 Freescale Semiconductor 8.4 Functional Description 8.4.1 Operational Modes Figure 8-8. Clock Switching Modes Entered from any state when MCU enters stop Returns to state that was active before MCU entered stop, unless RESET occurs while in stop. Stop PLL Bypassed External (PBE) PLL Engaged External (PEE) FLL Engaged External (FEE) FLL Engaged Internal (FEI) FLL Bypassed External (FBE) FLL Bypassed Internal (FBI) IREFS=1 CLKS=00 PLLS=0 IREFS=0 CLKS=00 PLLS=0 IREFS=1 CLKS=01 PLLS=0 IREFS=0 CLKS=10 PLLS=0 IREFS=0 CLKS=00 PLLS=1 IREFS=0 CLKS=10 PLLS=1 IREFS=0 CLKS=10 BDM Disabled and LP=1 IREFS=1 CLKS=01 PLLS=0 BDM Disabled and LP=1 Bypassed Low Power Internal (BLPI) Bypassed Low Power External (BLPE) BDM Enabled or LP=0 BDM Enabled or LP=0 BDM Enabled or LP=0 |
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