MC9S08DN60F1CLF datasheet(141/356 Pages) FREESCALE

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Chapter 8 Multi-Purpose Clock Generator (S08MCGV1)

MC9S08DN60 Series Data Sheet, Rev 3

Freescale Semiconductor

141

The nine states of the MCG are shown as a state diagram and are described below. The arrows indicate the

allowed movements between the states.

8.4.1.1

FLL Engaged Internal (FEI)

FLL engaged internal (FEI) is the default mode of operation and is entered when all the following

conditions occur:

•

CLKS bits are written to 00

•

IREFS bit is written to 1

•

PLLS bit is written to 0

•

RDIV bits are written to 000. Since the internal reference clock frequency should already be in the

range of 31.25 kHz to 39.0625 kHz after it is trimmed, no further frequency divide is necessary.

In FLL engaged internal mode, the MCGOUT clock is derived from the FLL clock, which is controlled by

the internal reference clock. The FLL clock frequency locks to 1024 times the reference frequency, as

selected by the RDIV bits. The MCGLCLK is derived from the FLL and the PLL is disabled in a low power

state.

8.4.1.2

FLL Engaged External (FEE)

The FLL engaged external (FEE) mode is entered when all the following conditions occur:

•

CLKS bits are written to 00

•

IREFS bit is written to 0

•

PLLS bit is written to 0

•

RDIV bits are written to divide reference clock to be within the range of 31.25 kHz to 39.0625 kHz

In FLL engaged external mode, the MCGOUT clock is derived from the FLL clock which is controlled by

the external reference clock. The external reference clock which is enabled can be an external

crystal/resonator or it can be another external clock source.The FLL clock frequency locks to 1024 times

the reference frequency, as selected by the RDIV bits. The MCGLCLK is derived from the FLL and the

PLL is disabled in a low power state.

8.4.1.3

FLL Bypassed Internal (FBI)

In FLL bypassed internal (FBI) mode, the MCGOUT clock is derived from the internal reference clock

and the FLL is operational but its output clock is not used. This mode is useful to allow the FLL to acquire

its target frequency while the MCGOUT clock is driven from the internal reference clock.

The FLL bypassed internal mode is entered when all the following conditions occur:

•

CLKS bits are written to 01

•

IREFS bit is written to 1

•

PLLS bit is written to 0

•

RDIV bits are written to 000. Since the internal reference clock frequency should already be in the

range of 31.25 kHz to 39.0625 kHz after it is trimmed, no further frequency divide is necessary.

MC9S08DN60F1CLF Datasheet(PDF) 141 Page - Freescale Semiconductor, Inc

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