PCIMX536AVV8B datasheet(116/180 Pages) FREESCALE

116 / 180 page

i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1

116

Freescale Semiconductor

Electrical Characteristics

The user must use level shifters for 5.0 V compatibility on the ATA interface. The i.MX53xA PATA

interface is 3.3 V compatible.

The use of bus buffers introduces delay on the bus and skew between signal lines. These factors make it

difficult to operate the bus at the highest speed (UDMA-5) when bus buffers are used. If fast UDMA mode

operation is needed, this may not be compatible with bus buffers.

Another area of attention is the slew rate limit imposed by the ATA specification on the ATA bus.

According to this limit, any signal driven on the bus should have a slew rate between 0.4 and 1.2 V/ns with

a 40 pF load. Not many vendors of bus buffers specify slew rate of the outgoing signals.

When bus buffers are used, the ata_data bus buffer is special. This is a bidirectional bus buffer, so a

direction control signal is needed. This direction control signal is ata_buffer_en. When its high, the bus

should drive from host to device. When its low, the bus should drive from device to host. Steering of the

signal is such that contention on the host and device tri-state busses is always avoided.

In the timing equations, some timing parameters are used. These parameters depend on the

implementation of the i.MX53xA PATA interface on silicon, the bus buffer used, the cable delay and

cable skew. Table 70 shows ATA timing parameters.

Table 70. PATA Timing Parameters

Name

Description

Value/

Contributing Factor1

Bus clock period (AHB_CLK_ROOT)

Peripheral clock frequency

(7.5 ns for 133 MHz clock)

ti_ds

Set-up time ata_data to ata_iordy edge (UDMA-in only)

UDMA0

UDMA1

UDMA2, UDMA3

UDMA4

UDMA5

15 ns

10 ns

7 ns

5 ns

4 ns

ti_dh

Hold time ata_iordy edge to ata_data (UDMA-in only)

UDMA0, UDMA1, UDMA2, UDMA3, UDMA4

UDMA5

5.0 ns

4.6 ns

tco

Propagation delay bus clock L-to-H to

ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack,

ata_data, ata_buffer_en

12.0 ns

tsu

Set-up time ata_data to bus clock L-to-H

8.5 ns

tsui

Set-up time ata_iordy to bus clock H-to-L

8.5 ns

thi

Hold time ata_iordy to bus clock H to L

2.5 ns

tskew1

Max difference in propagation delay bus clock L-to-H to any of following signals

ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack,

ata_data (write), ata_buffer_en

7ns

tskew2

Max difference in buffer propagation delay for any of following signals:

ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack,

ata_data (write), ata_buffer_en

Transceiver

tskew3

Max difference in buffer propagation delay for any of following signals ata_iordy,

ata_data (read)

Transceiver

PCIMX536AVV8B Datasheet(PDF) 116 Page - Freescale Semiconductor, Inc

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