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PCIMX536AVV8B Datasheet(PDF) 112 Page - Freescale Semiconductor, Inc |
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PCIMX536AVV8B Datasheet(HTML) 112 Page - Freescale Semiconductor, Inc |
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112 / 180 page  i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 112 Freescale Semiconductor Electrical Characteristics 4.7.11 One-Wire (OWIRE) Timing Parameters Figure 62 depicts the RPP timing, and Table 65 lists the RPP timing parameters. Figure 62. Reset and Presence Pulses (RPP) Timing Diagram Table 64. MLB Device 1024 Fs Timing Parameters Parameter Symbol Min Typ Max Units Comment MLBCLK Operating Frequency1 1 The MLB Controller can shut off MLBCLK to place MediaLB in a low-power state. fmck 45.056 49.152 49.2544 51.200 MHz Min: 1024*fs at 44.0 kHz Typ: 1024*fs at 48.0 kHz Max: 1024fs*fs at 48.1 kHz Max: 1024*fs PLL unlocked MLBCLK rise time tmckr —— 1 ns VIL TO VIH MLB fall time tmckf —— 1 ns VIH TO VIL MLBCLK cycle time tmckc —20.3 — ns — MLBCLK low time tmckl 6.5 6.1 7.7 7.3 —ns PLL unlocked MLBCLK high time tmckh 9.7 9.3 10.6 10.2 — — ns PLL unlocked MLBCLK pulse width variation tmpwv —— 0.7 ns pp Note2 2 Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge, measured in ns peak-to-peak (pp). MLBSIG/MLBDAT input valid to MLBCLK falling tdsmcf 1— — ns — MLBSIG/MLBDAT input hold from MLBCLK low tdhmcf 0— — ns — MLBSIG/MLBDAT output high impedance from MLBCLK low tmcfdz 0— tmckl ns — Bus Hold Time tmdzh 2— — ns Note3 3 The board must be designed to insure that the high-impedance bus does not leave the logic state of the final driven bit for this time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed. One-Wire bus One Wire Device Tx “Presence Pulse” (BATT_LINE) One-WIRE Tx “Reset Pulse” OW1 OW2 OW3 OW4 tR |
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