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PCIMX536AVV8B Datasheet(PDF) 110 Page - Freescale Semiconductor, Inc |
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PCIMX536AVV8B Datasheet(HTML) 110 Page - Freescale Semiconductor, Inc |
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110 / 180 page ![]() i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 110 Freescale Semiconductor Electrical Characteristics 4.7.9 LVDS Display Bridge (LDB) Module Parameters The LVDS interface complies with TIA/EIA 644-A standard. For more details, see TIA/EIA STANDARD 644-A, “Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits”. 4.7.10 MediaLB (MLB) Controller AC Timing Electrical Specifications This section describes the timing electrical information of the MediaLB Controller module. Figure 60 and Figure 61 show the timing of MediaLB Controller, and Table 63 and Table 64 lists the MediaLB controller timing characteristics. Figure 60. MediaLB Timing Figure 61. MediaLB Pulse Width Variation Timing 15Display RS down time DISP_CS_DOWN is predefined in REGISTER. Tdicdcs T DI_CLK ceil × () DISP_CS_DOWN_# DI_CLK_PERIOD --------------------------------------------------- = |
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