F28M36P63C2ZWTQ datasheet(39/202 Pages) TI

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F28M36P63B2, F28M36P63C2

F28M36P53B2, F28M36P53C2, F28M36P33B2, F28M36P33C2

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SPRS825 – OCTOBER 2012

SSI0, or I2C0 peripheral. (SSI0 and I2C0 are configured to work in Slave mode in this Boot Mode.) If the

boot pins are set to 0011b, the application code will be loaded from the Master Subsystem CAN interface.

Furthermore, if the boot pins are set to 0100b, the application code will be loaded through the Master

Subsystem Ethernet interface; the IOs used in this Boot Mode are compatible with the F28M35x device. If

the boot pins are set to 1001b or 1010b, then the application code will be loaded through the SSI0 or I2C0

interface, respectively. SSI0 and I2C0 loaders work in Master Mode in this boot mode. If the boot pins are

set to 1100b, then the application code will be loaded through the Master Subsystem Ethernet interface;

the IOs used in this Boot Mode are F28M36x IOs, which are available only in a BGA package.

Regardless of the type of boot mode selected, once the Master application code is resident in Master

Flash or RAM, the next step for the M-Bootloader is to branch to Master Flash or RAM. At that point, the

application code takes over control from the M-Bootloader, and the boot process continues as prescribed

by the application code. At this stage, the Master application program typically establishes communication

with the C-Bootloader, which by now, would have already initialized the Control Subsystem and forced the

C28x to go into Idle mode. To wake the Control Subsystem out of Idle mode, the Master application

issues the Master-to-Control-IPC-interrupt 1 (MTOCIPCINT1) . Once the data communication has been

established through the IPC, the boot process can now also continue on the Control Subsystem side.

The rest of the Control Subsystem boot process is controlled by the Master Subsystem application issuing

IPC instructions to the Control Subsystem, with the C-Bootloader interpreting the IPC commands and

acting on them to continue the boot process. At this stage, a boot mode for the Control Subsystem can be

established. The Control Subsystem boot modes are similar to the Master Subsystem boot modes, except

for the mechanism by which they are selected. The Control Subsystem boot modes are chosen through

the IPC commands from the Master application code to the C-Bootloader, which interprets them and acts

accordingly. The choices are, as above, to branch to already existing Control application code in Flash, to

branch to preloaded code in RAM (development mode), or to upload the Control application code from

one of several available peripherals (see Table 2-18). As before, once the Control application code is in

place (in Flash or RAM), the C-Bootloader branches to Flash or RAM, and from that point on, the

application code takes over.

Table 2-18. Control Subsystem Boot Mode Selection

Control Subsystem

MTOCIPCBOOTMODE

Description

Boot Modes

Upon receiving this command from the Master Subsystem, C-Boot

BOOT_FROM_RAM

0x0000 0001

ROM will branch to the Control Subsystem RAM entry point location

and start executing code from there.

Upon receiving this command, C-Boot ROM will branch to the

BOOT_FROM_FLASH

0x0000 0002

Control Subsystem FLASH entry point and start executing code from

there.