F28M36P63C2ZWTQ datasheet(65/202 Pages) TI

65 / 202 page

ONE OF 136

GPIO_MUX1 PINS

GPIOICR REG

GPIOAFSEL REG

GPIODEN REG

XRS

GPIOCSEL REG

GPAMUX1 REG

GPAMUX2 REG

SEL(1:0)

FROM C28 PERIPH 1-3

PERIPHERALS 1-3 REPRESENT A SET OF UP TO

THREE C28 PERIPHERALS SPECIFIC TO ONE I/O PIN

GPASET REG

GPACLEAR REG

GPATOGGLE REG

GPIOPUR REG

GPIOODR REG

C28 REG SET A

GREY LOGIC IS SPECIFIC TO

ONE DEVICE I/O PIN

OPEN

DRAIN

LOGIC

M3 REG SET A

QUAL

SYNC

C28SYSCLK

TO C28x CPU WAKE-UP FROM

A LOW POWER MODE

GPTRIP (12:1)

TO XINT, ECAP, EPWM

GPADIR REG

C28 REG SET A

GPACTRL REG

GPIODATA REG

GPIODIR REG

GPIOAPSEL REG

GPIOPCTL REG

GPIOIS REG

GPIOIBE REG

GPIOIEV REG

GPIOIM REG

GPIORIS REG

GPIOMIS REG

GPIOICR REG

GPIOAFSEL REG

GPIODEN REG

GPIO (A)

IRQ

TO/FROM M3 PERIPH 1-11

TO/FROM M3 PERIPH 12-15

GPIOCSEL REG

PERIPHERALS 1-15 REPRESENT A SET OF UP TO

15 M3 PERIPHERALS SPECIFIC TO ONE I/O PIN

GPIOPUR REG

GPIOODR REG

M3 REG SET A

PRIMARY

M3 REG SET A

ALT

‘1’

‘0’

OUTPUT

INPUT

A-S INTR REQUESTS TO M3

N/C

SEL(1:0)

6 SAMPLES

3 SAMPLES

ASYNC INPUT

TO C28 PERIPH 1-3

OUTPUT

DISABLED

AFTER RESET

NORMAL

AT RESET

SYNC INPUT

AT RESET

GPIO

AT RESET

SELECT M3

AT RESET

GPIO MODE

AT RESET

I/O DISABLED

AT RESET

OUTPUTS

INPUTS

SEL(1:0)

GPASEL1 REG

GPASEL2 REG

C28 REG SET A

(C28 GPIO)

GPADAT REG

N/C AT RESET

(M3 GPIO)

PULL-UP

DISABLED

ON RESET

PRIMARY

AT RESET

GPIOLOCK REG

GPIOCR REG

M3 REG SET A

GPIOAMSEL REG

M3 REG SET A

XCLKIN

GPIO63

ONLY

M3 CLOCKS

(USB ANALOG SIGNALS)

EACH I/O PIN HAS A

DEDICATED PAIR OF

BITS FOR MUX SELECT

EACH I/O PIN HAS A

DEDICATED PAIR OF

BITS FOR MUX SELECT

PULL UP

ENB

ORANGE LOGIC SHOWS

USB ANALOG FUNCTIONS

(APPLIES TO 4 PINS ONLY)

GPIOAMSEL REG

(4 PINS ONLY)

ANALOG USB

SIGNALS

GPTRIP1SEL REG

GPTRIP12SEL REG

…

GPI (63:0)

GREEN REGISTER SET A

SHOWN REPRESENTS 32

OF 136 GPIOs. THE

REMAINING 104 GPIOs

ARE CONTROLLED BY

SIMILAR REGISTER SETS

B, C, D AND E

BLUE REGISTER SET A

REPRESENTS 8 OF 136

GPIOs. REMAINING 128

GPIOs ARE CONTROLLED BY

SIMILAR REGISTER SETS

B, C, D, … Q, R, S

F28M36P63B2, F28M36P63C2

F28M36P53B2, F28M36P53C2, F28M36P33B2, F28M36P33C2

www.ti.com

SPRS825 – OCTOBER 2012

Figure 2-15. GPIO_MUX1 Pin Mapping Through Register Set A

Device Overview

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F28M36P63C2ZWTQ Datasheet(PDF) 65 Page - Texas Instruments

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