F28M36P63C2ZWTQ datasheet(24/202 Pages) TI

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F28M36P63B2, F28M36P63C2

F28M36P53B2, F28M36P53C2, F28M36P33B2, F28M36P33C2

SPRS825 – OCTOBER 2012

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2.3.5

Cortex™-M3 Vector Table

Each peripheral interrupt of Table 2-14 is assigned an address offset containing the location of the

peripheral interrupt handler (relative to the vector table base) for that particular interrupt (vector numbers

16–107).

Similarly, each exception interrupt of Table 2-15 (including Reset) is also assigned an address offset

containing the location of the exception interrupt handler (relative to the vector table base) for that

particular interrupt (vector numbers 1–15).

In addition to interrupt vectors, the vector table also contains the initial stack pointer value at table

location 0.

Following system reset, the vector table base is fixed at address 0x0000.0000. Privileged software can

write to the Vector Table Offset (VTABLE) register to relocate the vector table start address to a different

memory location, in the range 0x0000 0200 to 0x3FFF FE00. Note that when configuring the VTABLE

2.3.6

Cortex™-M3 Local Peripherals

The Cortex™-M3 local peripherals include two Watchdogs, an NMI Watchdog, four General-Purpose

Timers, four SSI peripherals, two CAN peripherals, five UARTs, two I2C peripherals, Ethernet, USB +

PHY, EPI, and µCRC (Cyclic Redundancy Check). The USB and EPI are accessible through the AHB Bus

(Advanced High-Performance Bus). The EPI peripheral is also accessible from the Control Subsystem.

The remaining peripherals are accessible through the APB Bus (Advanced Peripheral Bus). The APB and

AHB bus cycles originate from the CPU System Bus or the µDMA Bus via a bus bridge.

While the Cortex™-M3 CPU has access to all the peripherals, the µDMA has access to most, with the

exception of the µCRC, Watchdogs, NMI Watchdog, CAN peripherals, and the I2C peripheral. The

Cortex™-M3 peripherals connect to the Concerto™ device pins via GPIO_MUX1. Most of the peripherals

also generate event signals for the µDMA and the NVIC. The Watchdogs receive M3SWRST from the

NVIC (triggered by software) and send M3WDRST[1:0] reset requests to the Reset block. The NMI

Watchdog receives the M3NMI event from the NMI block and sends the M3NMIRST request to the Resets

block.

See Section 6.2 for more information on the Cortex™-M3 peripherals.

2.3.7

Cortex™-M3 Local Memory

The Local Memory includes Boot ROM; Secure Flash with Error Correction Code (ECC); Secure C0/C1

RAM with ECC; and C2/C3 RAM with Parity Error Checking. The Boot ROM and Flash are both

accessible through the I-CODE and D-CODE Buses. Flash registers can also be accessed by the

Cortex™-M3 CPU through the APB Bus. All Local Memory is accessible from the Cortex™-M3 CPU; the

C2/C3 RAM is also accessible by the µDMA.

Two types of error correction events can be generated during access of the Local Memory: uncorrectable

errors and single errors. The uncorrectable errors (including one from the Shared Memories) generate a

Bus Fault Exception to the Cortex™-M3 CPU. The less critical single errors go to the NVIC where they

can result in maskable interrupts to the Cortex™-M3 CPU.

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