F28M36P63C2ZWTQ datasheet(80/202 Pages) TI

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F28M36P63B2, F28M36P63C2

F28M36P53B2, F28M36P53C2, F28M36P33B2, F28M36P33C2

SPRS825 – OCTOBER 2012

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2.16.3 AIO_MUX1

The 12 pins of AIO_MUX1 can be selectively mapped through a dedicated set of registers to 12 analog

inputs for ADC1 peripheral, six analog inputs for Comparator peripherals, four General-Purpose Inputs, or

four General-Purpose Outputs. Note that while AIO_MUX1 has been named after the analog signals

passing through it, the GPIOs (here called AIOs) are still digital, although with fewer features than those in

the GPIO_MUX1 and GPIO_MUX2 blocks—for example, they do not offer pullups. On reset, all pins of the

AIO_MUX1 block are configured as analog inputs and the GPIO function is disabled. The AIO_MUX1

block is programmed through a separate set of registers from those used to program AIO_MUX2.

The multiple registers responsible for configuring the AIO_MUX1 pins are accessible by the C28x CPU

only. The top portion of Figure 2-16 shows Control Subsystem registers and muxing logic for the

associated 12 AIO pins. The AIOMUX1 register selects 1 of 12 possible analog input signals or 1 of 6

general-purpose AIO inputs. Other registers allow reading and writing of the 6 AIO bits, as well as setting

the direction for each of the bits (read or write). See Table 2-31 for the mapping of analog inputs and AIOs

to the 12 pins of AIO_MUX1.

AIO Mode 0 is chosen by setting selected odd bits of the AIOMUX1 register to ‘0’. AIO Mode 1 is chosen

by setting selected odd bits of the AIOMUX1 register to ‘1’. For example, setting bit 5 of the AIOMUX1

enabled at a time in the respective analog module). Currently, all even bits of the AIOMUX1 register are

“don’t cares”.

Table 2-31. AIO_MUX1 Pin Assignments (C28x AIO Modes)(1)(2)

Device Pin Name

C28x AIO Mode 0(3)

C28x AIO Mode 1(4)

ADC1INA0

–

ADC1INA0

ADC1INA2

AIO2

ADC1INA2, COMPA1

ADC1INA3

–

ADC1INA3

ADC1INA4

AIO4

ADC1INA4, COMPA2

ADC1INA6

AIO6

ADC1INA6, COMPA3

ADC1INA7

–

ADC1INA7

ADC1INB0

–

ADC1INB0

ADC2INB2

AIO10

ADC2INB2, COMPB1

ADC1INB3

–

ADC1INB3

ADC1INB4

AIO12

ADC1INB4, COMPB2

ADC2INB6

AIO14

ADC2INB6, COMPB3

ADC1INB7

–

ADC1INB7

(1)

Blank fields represent Reserved functions.

(2)

For each field with two pins (for example, ADC1INA2, COMPA1), only one pin should be enabled at a time; the other pin should be

disabled. Use registers inside the respective destination analog peripherals to enable or disable these inputs.

(3)

AIO Mode 0 represents digital general-purpose inputs or outputs.

(4)

AIO Mode 1 represents analog inputs for ADC1 or the Comparator module.

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