F28M36P63C2ZWTQ datasheet(19/202 Pages) TI

19 / 202 page

F28M36P63B2, F28M36P63C2

F28M36P53B2, F28M36P53C2, F28M36P33B2, F28M36P33C2

www.ti.com

SPRS825 – OCTOBER 2012

2.3

Master Subsystem

The Master Subsystem includes the Cortex™-M3 CPU, µDMA, Nested Vectored Interrupt Controller

(NVIC), Cortex™-M3 Peripherals, and Local Memory. Additionally, the Cortex™-M3 CPU and µDMA can

access the Control Subsystem through Shared Resources: IPC (CPU only), Message RAM, and Shared

RAM; and read ADC Result Registers via the Analog Common Interface Bus. The Master Subsystem can

also receive events from the NMI block and send events to the Resets block.

Figure 2-1 shows the Master Subsystem.

2.3.1

Cortex™-M3 CPU

The 32-bit Cortex™-M3 processor offers high performance, fast interrupt handling, and access to a variety

of communication peripherals (including Ethernet and USB). The Cortex™-M3 features a Memory

Protection Unit (MPU) to provide a privileged mode for protected operating system functionality. A bus

bridge adjacent to the MPU can route program instructions and data on the I-CODE and D-CODE buses

that connect to the Boot ROM and Flash. Other data is typically routed through the Cortex™-M3 System

Bus connected to the local RAMs. The System Bus also goes to the Shared Resources block (also

accessible by the Control Subsystem) and to the Analog Subsystem through the Analog Common

Interface Bus (ACIB). Another bus bridge allows bus cycles from both the Cortex™-M3 System Bus and

those of the µDMA bus to access the Master Subsystem peripherals (via the APB bus or the AHP bus).

Most of the interrupts to the Cortex™-M3 CPU come from the Nested Vectored Interrupt Controller

(NVIC), which manages the interrupt requests from peripherals and assigns handling priorities. There are

also several exceptions generated by Cortex™-M3 CPU that can return to the Cortex™-M3 as interrupts

after being prioritized with other requests inside the NVIC. In addition to programmable priority interrupts,

there are also three levels of fixed-priority interrupts of which the highest priority, level-3, is given to

M3PORRST and M3SYSRST resets from the Resets block. The next highest priority, level-2, is assigned

to the M3NMIINT, which originates from the NMI block. The M3HRDFLT (Hard Fault) interrupt is assigned

to level-1 priority, and this interrupt is caused by one of the error condition exceptions (Memory

Management, Bus Fault, Usage Fault) escalating to Hard Fault because they are not enabled or not

properly serviced.

The Cortex™-M3 CPU has two low-power modes: Sleep and Deep Sleep.

2.3.2

Cortex™-M3 Core Hardware Logic Built-In Test (LBIST)

The Concerto™ microcontroller Cortex™-M3 CPU core includes a Logic Built-In Self Test (LBIST)

controller for testing the CPU core logic for errors. Tests are initiated by software whenever convenient (at

start-up, idle, and so on), which allows for periodic logic tests to ensure that the CPU core logic is working

correctly. During a test cycle, all interrupts are logged by the LBIST controller and re-issued after the test

cycle completes to ensure that no interrupts are missed. In the event of a logic error, the LBIST controller

generates an NMI on both cores to signal that an error has been detected. This action allows for the

software to gracefully handle any detected logic errors.

Device Overview

Submit Documentation Feedback

F28M36P63C2ZWTQ Datasheet(PDF) 19 Page - Texas Instruments

F28M36P63C2ZWTQ Datasheet(HTML) 19 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL