R5F110ME datasheet(116/153 Pages) RENESAS

116 / 153 page

RL78/L1C

3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 °C)

R01DS0192EJ0200 Rev. 2.00

Page 116 of 149

Feb 21, 2014

Note 1.

Transfer rate in the SNOOZE mode is 4,800 bps only.

Note 2.

Use it with VDD

 Vb.

Note 3.

The following conditions are required for low voltage interface.

2.4 V

 VDD  2.7 V:

MAX. 2.6 Mbps

Note 4.

The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:

HS (high-speed main) mode:

24 MHz (2.7 V

 VDD  3.6 V)

16 MHz (2.4 V

 VDD  3.6 V)

Caution

Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for the TxDq

pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the

DC characteristics with TTL input buffer selected.

Remark 1. Vb[V]: Communication line voltage

Remark 2.

q: UART number (q = 0 to 3), g: PIM and POM number (g = 0 to 3)

Remark 3.

fMCK: Serial array unit operation clock frequency

(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,

n: Channel number (mn = 00 to 03, 10 to 13)

(5)

Communication at different potential (1.8 V, 2.5 V) (UART mode)

(TA = -40 to +105 °C, 2.4 V  VDD  3.6 V, VSS = 0 V)

(1/2)

Parameter

Symbol

Conditions

HS (high-speed main) Mode

Unit

MIN.

MAX.

Transfer rate Notes 1, 2

Reception

2.7 V

 VDD  3.6 V,

2.3 V

 Vb  2.7 V

fMCK/12 Note 1

bps

Theoretical value of the maximum transfer rate

fMCK = fCLK Note 4

2.0

Mbps

1.8 V

 VDD  3.3 V,

1.6 V

 Vb  2.0 V

fMCK/12 Notes 1, 2, 3

bps

Theoretical value of the maximum transfer rate

fMCK = fCLK Note 4

1.3

Mbps

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