AT89LP51RB2 datasheet(57/254 Pages) ATMEL

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3722A–MICRO–10/11

AT89LP51RB2/RC2/IC2 Preliminary

Figure 8-2.

Interrupt Recovery from Power-down (PWDEX = 0)

8.2.2

Reset Recovery from Power-down

The wake-up from Power-down through an external reset is similar to the interrupt with

PWDEX = “1”. At the rising edge of RST, Power-down is exited, the oscillator is restarted, and

an internal timer begins counting as shown in Figure 8-3. The internal clock will not be allowed to

propagate to the CPU until after the timer has timed out. The time-out period is controlled by the

Start-up Timer Fuses. (See Table 7-1 on page 52). If RST returns low before the time-out, a two

clock cycle internal reset is generated when the internal clock restarts. Otherwise, the device will

remain in reset until RST is brought low.

Figure 8-3.

Reset Recovery from Power-down (POL = 1)

8.3

Reducing Power Consumption

Several possibilities need consideration when trying to reduce the power consumption in an

8051-based system.

• Idle or Power-down mode should be used as often as possible with interrupts waking up the

system to handle specific tasks

• All un-needed peripheral functions should be disabled

•The System Clock Prescaler can scale down the operating frequency during periods of low

demand (See “System Clock Prescaler” on page 47.)

• The ALE output can be disabled by setting AO in AUXR, thereby also reducing EMI

•For AT89LP51IC2, switch the system clock from a high power oscillator like XTALA to a lower

power oscillator like the internal 8 MHz oscillator during periods when frequency accuracy is

not as important.

PWD

INT1

XTAL1

Internal

Clock

PWD

RST

XTAL1

tSUT

Internal

Clock

Internal

Reset

AT89LP51RB2 Datasheet(PDF) 57 Page - ATMEL Corporation