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UPSD3312D Datasheet(PDF) 133 Page - STMicroelectronics |
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UPSD3312D Datasheet(HTML) 133 Page - STMicroelectronics |
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133 / 272 page ![]() Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) UPSD33xx I2C interface Doc ID 9685 Rev 7 133/272 Table 81. S1SETUP register bit definition Table 82. Number of I2C bus samples taken after 1-to-0 transition on SDA (START condition) Table 83. Start condition hold time Table 84 provides recommended settings for S1SETUP based on various combinations of fOSC and fSCL. Note that the “Total Sample Period” times in Table 83 are typically slightly less than the minimum START condition hold time, tHLDSTA for a given I 2C bus speed. Note: Important: The SCL bit rate fSCL must first be determined by bits CR[2:0] in the SFR S1CON before a value is chosen for SMPL_SET[6:0] in the SFR S1SETUP. Bit Symbol R/W Function 7 EN_SS R/W Enable Sample Setup EN_SS = 1 will force the SIOE to sample(1) a START condition on the bus the number of times specified in SMPL_SET[6:0]. EN_SS = 0 means the SIOE will sample(1) a START condition only one time, regardless of the contents of SMPL_SET[6:0]. 1. Sampling SCL and SDA lines begins after '1'-to-'0' transition on SDA occurred while SCL is high. Time between samples is 1/fOSC. 6:0 SMPL_SET [6:0] – Sample Setting Specifies the number of bus samples((1) taken during a START condition. See Table 82 on page 133 for values. Contents of S1SETUP Resulting value for S1SETUP Resulting number of samples taken after 1-to-0 on SDA Line SS_EN bit SMPL_SET[6:0] 0 XXXXXXXb 00h (default) 1 1 0000000b 80h 1 1 0000001b 81h 2 1 0000010b 82h 3 ... ... ... ... 1 0001011b 8Bh 12 1 0010111b 97h 24 ... ... ... ... 1 1111111b FFh 128 I2C bus speed Range of I2C clock speed (fSCL) Minimum START condition hold time (tHLDSTA) Standard Up to 100kHz 4000ns Fast 101kHz to 400kHz 600ns High 401kHz to 833kHz(1) 1. 833kHz is maximum for UPSD33xx devices. 160ns |
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