DSP56362AD datasheet(43/168 Pages) MOTOROLA

43 / 168 page

Specifications

Internal Clocks

MOTOROLA

DSP56362 Advance Information

2-5

INTERNAL CLOCKS

Table 2-4 Internal Clocks, CLKOUT

Characteristics

Symbol

Expression1, 2

Min

Typ

Max

Internal operation frequency and

CLKOUT with PLL enabled

f—

(Ef

× MF)/

(PDF

× DF)

—

Internal operation frequency and

CLKOUT with PLL disabled

—

Ef/2

—

Internal clock and CLKOUT high

period

• With PLL disabled

—

ETC

—

• With PLL enabled and

≤ 4

0.49

× ETC ×

PDF

× DF/MF

—

0.51

× ETC ×

PDF

× DF/MF

• With PLL enabled and

MF > 4

0.47

× ETC ×

PDF

× DF/MF

—

0.53

× ETC ×

PDF

× DF/MF

Internal clock and CLKOUT low

period

• With PLL disabled

—

ETC

—

• With PLL enabled and

≤ 4

0.49

× ETC ×

PDF

× DF/MF

—

0.51

× ETC ×

PDF

× DF/MF

• With PLL enabled and

MF > 4

0.47

× ETC ×

PDF

× DF/MF

—

0.53

× ETC ×

PDF

× DF/MF

Internal clock and CLKOUT cycle

time with PLL enabled

—

ETC × PDF ×

DF/MF

—

Internal clock and CLKOUT cycle

time with PLL disabled

—2

× ETC

—

Instruction cycle time

ICYC

—TC

—

Notes: 1.

DF = Division Factor

Ef = External frequency

ETC = External clock cycle

MF = Multiplication Factor

PDF = Predivision Factor

TC = internal clock cycle

See the PLL and Clock Generation section in the DSP56300 Family Manual for a detailed discussion

of the PLL.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

DSP56362AD Datasheet(PDF) 43 Page - Motorola, Inc

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