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DSP56362AD Datasheet(PDF) 89 Page - Motorola, Inc |
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DSP56362AD Datasheet(HTML) 89 Page - Motorola, Inc |
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89 / 168 page  Specifications Parallel Host Interface (HDI08) Timing MOTOROLA DSP56362 Advance Information 2-51 PARALLEL HOST INTERFACE (HDI08) TIMING Table 2-20 Host Interface (HDI08) Timing1, 2 No. Characteristics3 Expression 100 MHz Unit Min Max 317 Read data strobe assertion width 4 HACK read assertion width TC + 9.9 19.9 — ns 318 Read data strobe deassertion width 4 HACK read deassertion width —9.9 — ns 319 Read data strobe deassertion width4 after “Last Data Register” reads5,6, or between two consecutive CVR, ICR, or ISR reads7 HACK deassertion width after “Last Data Register” reads5,6 2.5 × TC + 6.6 31.6 — ns 320 Write data strobe assertion width 8 HACK write assertion width —13.2 — ns 321 Write data strobe deassertion width8 HACK write deassertion width • after ICR, CVR and “Last Data Register” writes5 2.5 × TC + 6.6 31.6 — ns • after IVR writes, or • after TXH:TXM writes (with HBE=0), or after TXL:TXM writes (with HBE=1) • 16.5 — 322 HAS assertion width —9.9 — ns 323 HAS deassertion to data strobe assertion9 —0.0 — ns 324 Host data input setup time before write data strobe deassertion8 Host data input setup time before HACK write deassertion —9.9 — ns 325 Host data input hold time after write data strobe deassertion8 Host data input hold time after HACK write deassertion —3.3 — ns 326 Read data strobe assertion to output data active from high impedance4 HACK read assertion to output data active from high impedance —3.3 — ns 327 Read data strobe assertion to output data valid 4 HACK read assertion to output data valid —— 24.2 ns Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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