CP3SP33SMSSLASHNOPB datasheet(314/407 Pages) TI1

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CP3SP33

SNOSCW5 – MAY 2013

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RTCRD

30.4.7 RTC Counter Load Register (RTCLD)

The RTCLD register is a 32-bit, read/write register used to load a new value into the 32-bit counter. The

counter will be loaded on the next rising edge of its input clock (prescaler output). When the RTCLD

RTCLD register is loaded into the counter. When the RTCLD register is read, it returns the last value that

was written to it. At system reset or power-on reset, this register is cleared to 0000 0000h.

RTCLD

30.4.8 RTC Compare Register 1 (RTCCMP1)

The RTCCMP register is a 16-bit, read/write register which holds a value compared with the contents of

the 16-bit prescaler. When this register is loaded, the RTUCP1 bit in the RTUDST register is set, and the

bit remains set until the up- dated RTCCMP1 register value takes effect. When the contents of the

RTCCMP1 register matches the contents of the prescaler, the prescaler will be cleared on the next rising

edge of its input clock (divider output), and the RTCEVT1 bit in the RTCEIST register is set. If the

RTCIEN1 bit in the RTCIEN register is set, an interrupt is asserted. System reset does not affect this

RTCCMP1

30.4.9 RTC Compare Register 2 (RTCCMP2)

The RTCCMP2 register is a 32-bit, read/write register which holds a value compared with the contents of

the 32-bit counter. When this register is loaded, the RTUCP2 bit in the RTUDST register is set, and the bit

remains set until the up- dated RTCCMP2 register value takes effect. When the contents of the RTCCMP2

RTCIEN2 bit in the RTCIEN register is set, an interrupt is asserted. System reset does not affect this

RTCCMP2

30.4.10 RTC Compare Register 3 (RTCCMP3)

The RTCCMP3 register is a 32-bit, read/write register which holds a value compared with the contents of

the 32-bit counter. When this register is loaded, the RTUCP3 bit in the RTUDST register is set, and the bit

remains set until the updated RTCCMP3 register value takes effect. When the contents of the RTCCMP3

RTCIEN3 bit in the RTCIEN register is set, an interrupt is asserted. System reset does not affect this

RTCCMP3

314

Timing and Watchdog Module

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CP3SP33SMS/NOPB Datasheet(PDF) 314 Page - Texas Instruments