iPEM

4.8 Gb SDRAM-DDR2

AS4DDR264M72PBG1

AS4DDR264M72PBG1

Rev. 3.1 01/10

6

Micross Components reserves the right to change products or specifications without notice.

NOTES:

1. Applying power; if CKE is maintained below 0.2 x VCC, outputs

remain disabled. To guarantee RTT (ODT resistance) is off,

VREF

must be valid and a low level must be applied to the ODT ball (all

other inputs may be undefined, I/Os and outputs must be less

than VCC during voltage ramp time to avoid DDR2 SDRAM

device

following two sets of conditions (A or B) must be met to obtain a

stable supply state (stable supply defined as VCC, VREF,

and VTT are between their minimum and maximum values as

stated in DC Operating Conditions table):

A. (single power source) The VCC voltage ramp from 300mV to

VCC(MIN) must take no longer than 200ms.

• All VCC are driven from a single power converter output

• VTT is limited to 0.95V MAX

to VCC/2 during supply ramp time.

• VCC > VREF at all times

2. CKE requires LVCMOS input levels prior to state T0 to ensure

DQs are High-Z during device power-up prior to VREF being

stable. After state T0, CKE is required to have SSTL_18 input

levels. Once CKE transitions to a high level, it must stay HIGH for

the duration of the initialization sequence.

3. A10 = PRECHARGE ALL, CODE = desired values for mode

registers (bank addresses are required to be decoded).

4. For a minimum of 200μs after stable power and clock (CK, CK#),

apply NOP or DESELECT commands, then take CKE HIGH.

5. Issue a LOAD MODE command to the EMR(2). To issue an EMR(2)

command, provide LOW to BA0, and provide HIGH to BA1; set

register E7 to “0” or “1” to select appropriate self refresh rate;

remaining EMR(2) bits must be “0” (see “Extended Mode Register

2 (EMR2)” on page 84 for all EMR(2) requirements).

6. Issue a LOAD MODE command to the EMR(3). To issue an EMR(3)

command, provide HIGH to BA0 and BA1; remaining EMR(3) bits

must be “0.” See “Extended Mode Register 3 (EMR 3)” on page 13

for all EMR(3) requirements.

7. Issue a LOAD MODE command to the EMR to enable DLL. To issue

a DLL ENABLE command, provide LOW to BA1 and A0; provide

HIGH to BA0; bits E7, E8, and E9 can be set to “0” or “1;” Austin

recommends setting them to “0;” remaining EMR bits must be “0.

”See “Extended Mode Register (EMR)” on page 10 for all EMR

requirements.

8. Issue a LOAD MODE command to the MR for DLL RESET. 200

cycles of clock input is required to lock the DLL. To issue a DLL

RESET, provide HIGH to A8 and provide LOW to BA1 and BA0;

CKE must be HIGH the entire time the DLL is resetting; remaining

MR bits must be “0.” See “Mode Register (MR)” on page 7 for all

MR requirements.

9. Issue PRECHARGE ALL command.

10. Issue two or more REFRESH commands.

11. Issue a LOAD MODE command to the MR with LOW to A8 to

initialize device operation (that is, to program operating parameters

without resetting the DLL). To access the MR, set BA0 and BA1

LOW; remaining MR bits must be set to desired settings. See

“Mode Register (MR)” on page 7 for all MR requirements.

12. Issue a LOAD MODE command to the EMR to enable OCD

default by setting bits E7, E8, and E9 to “1,” and then setting all

other desired parameters. To access the EMR, set BA0 LOW

and BA1 HIGH (see “Extended Mode Register (EMR)” on page 10

for all EMR requirements).

13. Issue a LOAD MODE command to the EMR to enable OCD exit by

setting bits E7, E8, and E9 to “0,” and then setting all other desired

parameters. To access the extended mode registers, EMR, set

BA0 LOW and BA1 HIGH for all EMR requirements.

14. The DDR2 SDRAM is now initialized and ready for normal

operation 200 clock cycles after the DLL RESET at Tf0.

15. DM represents UDM, LDM collectively for each die x16

configuration. DQS represents UDQS, USQS, LDQS, LDQS for

each die x16 configuration. DQ represents DQ0-DQ15 for each

die x16 configuration.

16. Wait a minimum of 400ns then issue a PRECHARGE ALL

command.