iPEM

4.8 Gb SDRAM-DDR2

AS4DDR264M72PBG1

AS4DDR264M72PBG1

Rev. 3.1 01/10

14

Micross Components reserves the right to change products or specifications without notice.

TABLE 3 - TRUTH TABLE - DDR2 COMMANDS

Note: 1. All DDR2-SDRAM commands are defined by staes of CS#, RAS#, CAS#, WE#, and CKE a the

rising edge of the clock.

2. Bank addresses (BA) BA2-BA0 determine which bank is to be operated upon. BA during a LM

command selects which mode register is programmed.

3. Burst reads or writes at BL=4 cannot be terminated or interrupted.

4. The power down mode does not perform any REFRESH operations. The duration of power down

is therefore limited by the refresh requirements outlined in the AC parametric section.

5. The state of ODT does not effect the states described in this table. The ODT function is not available

during self refresh. See “On Die Termination (ODT)” for details.

6. “X” means “H or L” (but a defined logic level)

7. Self refresh exit is asynchronous.

BA0

A11

LOAD MODE

H

H

LLLL

BA

2

REFRESH

H

H

L

L

L

H

XXXX

SELF-REFRESH Entry

H

L

L

L

L

H

XXXX

H

XXX

L

HHH

Single Bank Precharge

HH

L

L

H

L

X

X

L

X

2

All banks PRECHARGE

HH

L

L

H

L

X

X

H

X

Bank Activate

HH

L

L

H

L

BA

WRITE

HH

L

L

H

L

BA

Column

Address

L

Column

Address

2,3

WRITE with auto precharge

HH

L

H

L

L

BA

Column

Address

H

Column

Address

2,3

READ

H

H

LHLH

BA

Column

Address

L

Column

Address

2,3

READ with auto precharge

H

H

LHLH

BA

Column

Address

L

Column

Address

2,3

NO OPERATION

H

X

L

H

H

H

XXXX

Device DESELECT

H

X

H

XXXXXXX

H

XXX

L

HHH

H

XXX

L

HHH

Function

CS#

RAS#

A10

A9-A0

Notes

Previous

Cycle

Current

Cycle

CAS#

WE#

BA2 thru

A12

CKE

POWER-DOWN exit

L

H

XXXX

4

POWER-DOWN entry

H

L

XXXX

4

7

SELF-REFRESH exit

LH

X

OP CODE

ROW ADDRESS

XXX