iPEM

4.8 Gb SDRAM-DDR2

AS4DDR264M72PBG1

AS4DDR264M72PBG1

Rev. 3.1 01/10

10

Micross Components reserves the right to change products or specifications without notice.

FIGURE 7 – EXTENDED MODE REGISTER DEFINITION

EXTENDED MODE REGISTER (EMR)

The extended mode register controls functions beyond those

controlled by the mode register; these additional functions are

DLL enable/disable, output drive strength, on die termination

(ODT) (RTT), posted AL, off-chip driver impedance calibration

(OCD), DQS# enable/disable, RDQS/RDQS# enable/disable,

and output disable/enable. These functions are controlled via the

bits shown in Figure 7. The EMR is programmed via the LOAD

MODE (LM) command and will retain the stored information

until it is programmed again or the device loses power.

Reprogramming the EMR will not alter the contents of the memory

array, provided it is performed correctly.

The EMR must be loaded when all banks are idle and no bursts

are in progress, and the controller must wait the specified time

t

MRD before initiating any subsequent operation. Violating either

of these requirements could esult in unspecified operation.

DLL

Out

A9

A7 A6 A5 A4 A3

A8

A2

A1 A0

Extended mode

register (Ex)

Address bus

97

6

5

4

3

82

1

0

A10

A12 A11

BA0

BA1

10

11

12

n

0

14

E1

0

1

Output Drive Strength

Full

Reduced

Posted CAS# Additive Latency (AL)

0

1

2

3

4

5

6

Reserved

E3

0

1

0

1

0

1

0

1

E4

0

0

1

1

0

0

1

1

E5

0

0

0

0

1

1

1

1

0

1

DLL Enable

Enable (normal)

Disable (test/debug)

E0

15

E11

0

1

RDQS Enable

No

Yes

OCD Program

An

2

ODS

DQS#

E10

0

1

DQS# Enable

Enable

Disable

RDQS

75

150

50

E2

0

1

0

1

E6

0

0

1

1

0

1

Outputs

Enabled

Disabled

E12

0

1

0

1

Mode Register Set

Mode register (MR)

Extended mode register (EMR)

Extended mode register (EMR2)

Extended mode register (EMR3)

E15

0

0

1

1

E14

MRS

BA2

1

16

0

OCD Operation

OCD exit

Reserved

Reserved

Reserved

Enable OCD defaults

E7

0

1

0

0

1

E8

0

0

1

0

1

E9

0

0

0

1

1

Notes:

1.During initialization, all three bits must be set to “1” for OCD default state, then must be set to “0” before

initialization is finished, as detailed in the initialization procedure.

2.E13 (A13) must be programmed to “0” and is reserved for future use.

3.E16 must be programmed to “0” and is reserved for future use.

4.Not all AL options are supported in any individual speed grade.

2

(100%)

(40-60%)

3

2

4