iPEM

4.8 Gb SDRAM-DDR2

AS4DDR264M72PBG1

AS4DDR264M72PBG1

Rev. 3.1 01/10

9

Micross Components reserves the right to change products or specifications without notice.

CAS LATENCY (CL)

The CAS latency (CL) is defined by bits M4-M6, as shown

in Figure 5. CL is the delay, in clock cycles, between the

registration of a READ command and the availability of the first

bit of output data. The CL can be set to 3, 4, 5, 6 or 7 clocks,

depending on the speed grade option being used.

DDR2 SDRAM does not support any half-clock latencies.

Reserved states should not be used as unknown operation

or incompatibility with future versions may result.

DDR2 SDRAM also supports a feature called posted CAS

additive latency (AL). This feature allows the READ command

internal command to the DDR2 SDRAM by AL clocks.

Examples of CL = 3 and CL = 4 are shown in Figure 6; both

assume AL = 0. If a READ command is registered at clock

edge n, and the CL is m clocks, the data will be available

nominally coincident with clock edge n+m (this assumes

AL = 0).

FIGURE 6 - CAS LATENCY (CL)

Notes:

1. BL = 4.

2. Posted CAS# additive latency (AL) = 0.

Extended Mode Register (EMR)

DO

n + 3

DO

n + 2

DO

n + 1

CK

CK#

Command

DQ

DQS, DQS#

CL = 3 (AL = 0)

READ

T0

T1

T2

Don’t care

Transitioning data

NOP

NOP

NOP

DO

n

T3

T4

T5

NOP

NOP

T6

NOP

DO

n + 3

DO

n + 2

DO

n + 1

CK

CK#

Command

DQ

DQS, DQS#

CL = 4 (AL = 0)

READ

T0

T1

T2

NOP

NOP

NOP

DO

n

T3

T4

T5

NOP

NOP

T6

NOP