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AS4DDR264M72PBG1-3/XT Datasheet(PDF) 24 Page - Micross Components |
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AS4DDR264M72PBG1-3/XT Datasheet(HTML) 24 Page - Micross Components |
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24 / 28 page  iPEM 4.8 Gb SDRAM-DDR2 AS4DDR264M72PBG1 AS4DDR264M72PBG1 Rev. 3.1 01/10 24 Micross Components reserves the right to change products or specifications without notice. AC OPERATING SPECIFICATIONS -3 -38 -5 667MHz 533MHz 400MHz Parameter Symbol MIN MAX MIN MAX MIN MAX Units Clock Cycle Time CL=5 tCKAVG 38 ns CL=4 tCKAVG 3.75 8 3.75 8 5 8 ns CL=3 tCKAVG 585858 ns Clock High Time tCHAVG 0.48 0.52 0.48 0.52 0.48 0.52 tCK Clock Low Time tCLAVG 0.48 0.52 0.48 0.52 0.48 0.52 tCK Half Clock Period Min of tHP tCH,tCL tCH,tCL tCH,tCL ps Clock Jitter - Period tJITPER -125 125 -125 125 -125 125 ps Clock Jitter - Half Period tJIT DUTY -125 125 -125 125 -150 150 ps Clock Jitter - Cycle to Cycle tJITCC ps Cumulative Jitter error, 2 Cycles tERR2PER -175 175 -175 175 -175 175 ps Cumulative Jitter error, 4 Cycles tERR4PER -250 250 -250 250 -250 250 ps Cumulative Jitter error, 6-10 Cycles tERR10PER -350 350 -350 350 -350 350 ps Cumulative Jitter error, 11-50 Cycles tERR50PER -450 450 -450 450 -450 450 ps DQ hold skew factor tQHS - 340 - 400 - 450 ps DQ output access time from CK/CK\ tAC -450 450 -500 500 -600 600 ps Data-out High-Z window from CK/CK\ tHZ tAC(MAX) tAC(MAX) tAC(MAX) ps DQS Low-Z window from CL/CK\ tLZ1 tAC(MIN) tAC(MAX) tAC(MIN) tAC(MAX) tAC(MIN) tAC(MAX) ps DQ Low-Z window from CK/CK\ tLZ2 2*tAC(MIN) tAC(MAX) 2*tAC(MIN) tAC(MAX) 2*tAC(MIN) tAC(MAX) ps DQ and DM input setup time relative to DQS tDSJEDEC 100 100 150 ps DQ and DM input hold time relative to DQS tDHJEDEC 175 225 275 ps DQ and DM input pulse width (for each input) tDIPW 0.35 0.35 0.35 tCK Data Hold skew factor tQHS 340 400 450 ps DQ-DQS Hold, DQS to first DQ to go non valid, per access tQH tHP-tQHS tHP-tQHS tHP-tQHS ps Data valid output window (DVW) tDVW tQH-tDQSQ tQH-tDQSQ tQH-tDQSQ ps DQS input-high pulse width tDQSH 0.35 0.35 0.35 tCK DQS input-low pulse width tDQSL 0.35 0.35 0.35 tCK DQS output access time from CK/CK\ tDQSCK -400 400 -400 400 -450 450 ps DQS falling edge to CK rising - setup time tDSS 0.2 0.2 0.2 tCK DQS falling edge from CK rising-hold time tDSH 0.2 0.2 0.2 tCK DQS-DQ skew, DQS to last DQ valid, per group, per access tDQSQ 240 300 350 ps DQS READ preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK DQS READ postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK WRITE preamble setup time tWPRES 0 0 0 ps DQS WRITE preamble tWPRE 0.35 0.35 0.35 tCK DQS WRITE postamble tWPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK Positive DQS latching edge to associated Clock edge tDQSS -0.25 0.25 -0.25 0.25 -0.25 0.25 tCK WRITE command to first DQS latching transition WL-tDQSS WL+tDQSS WL-tDQSS WL+tDQSS WL-tDQSS WL+tDQSS tCK 250 250 250 |
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