iPEM

4.8 Gb SDRAM-DDR2

AS4DDR264M72PBG1

AS4DDR264M72PBG1

Rev. 3.1 01/10

1

Micross Components reserves the right to change products or specifications without notice.

64Mx72 DDR2 SDRAM w/ SHARED CONTROL BUS

iNTEGRATED Plastic Encapsulated Microcircuit

FEATURES

DDR2 Data rate = 667, 533, 400

Available in Industrial, Enhanced and Military Temp

Package:

Differential data strobe (DQS, DQS#) per byte

Internal, pipelined, double data rate architecture

4n-bit prefetch architecture

DLL for alignment of DQ and DQS transitions with

clock signal

Eight internal banks for concurrent operation

(Per DDR2 SDRAM Die)

Programmable Burst lengths: 4 or 8

Auto Refresh and Self Refresh Modes (I/T Version)

On Die Termination (ODT)

Adjustable data – output drive strength

Programmable CAS latency: 3, 4, 5, 6 or 7

Posted CAS additive latency: 0, 1, 2, 3, 4 or 5

Write latency = Read latency - 1* tCK

Organized as 64M x 72

Weight: AS4DDR264M72PBG1 ~ 2.0 grams typical

NOTE: Self Refresh Mode available on Industrial and Enhanced temp. only

BENEFITS

61% Space Savings

55% I/O reduction vs Individual package

approach

Reduced part count

Reduced trace lengths for lower parasitic

capacitance

Suitable for hi-reliability applications

Upgradable to 128M x 72 density in future

Pin/Function equivalent to White

W3H64M72E-xBSx

FUNCTIONAL BLOCK DIAGRAM

ODT

VRef

VCC

VCCQ

VSS

VSSQ

VCCL

VSSDL

VCCL

VSSDL

VCCL

VSSDL

VCCL

VSSDL

VCCL

VSSDL

WE\

RAS\

CAS\

CKE\

Ax, BA0-2

UDMx, LDMx

UDSQx,UDSQx\

LDSQx, LDSQx\

ODT

CKx,CKx\

A

BC

D

DQ0-15

DQ16-31

DQ32-47

DQ48-63

A

B

C

D

DQ64-71

VCCQ

VCCQ

VCCQ

VCCQ

VSSQ

VSSQ

VSSQ

VSSQ

VSSQ

CS\

LDM4

UDM4

ODT

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

Configuration Addressing

Parameter

64 Meg x 72

Configuration

8 Meg x 16 x 8 Banks

Refresh Count

8K

Row Address

A0 A12 (8k)

Bank Address

BA0 BA2 (8)

Column Address

A0 A9 (1K)