iPEM

4.8 Gb SDRAM-DDR2

AS4DDR264M72PBG1

AS4DDR264M72PBG1

Rev. 3.1 01/10

23

Micross Components reserves the right to change products or specifications without notice.

DDRII ICC SPECIFICATIONS AND CONDITIONS

Parameter

Symbol

Units

Operating Current: One bank active-precharge

Precharge POWER-DOWN current

Precharge quiet STANDBY current

Precharge STANDBY current

Active POWER-DOWN current

Active STANDBY current

Operating Burst WRITE current

Operating Burst READ current

Burst REFRESH current

Self REFRESH current

Operating bank Interleave READ current:

1700

1600

mA

1500

mA

1250

1100

1000

mA

250

200

mA

850

700

600

mA

300

All banks open; tCK=tCK(ICC), tRAS MAX(ICC),

tRP=tRP(ICC); CKE is HIGH, CS\ is HIGH between valid

commands; Other control and address bus inputs are

switching; Data bus inputs are switching

ICC5

ICC6

CK and CK\ at 0V; CKE </=0.2V; Other contro, address and

data inputs are floating

ICC3N

ICC4W

ICC4R

ICC7

All banks idle; tCK-=tCK(ICC); CKE is HIGH, CS\ is HIGH;

Other control and address bus inputs are switching; Data bus

inputs are switching

600

MRS[12]=1

330

50

50

35

250

275

220

mA

150

ICC2Q

All banks idle; tCK=tCK(ICC); CKE is HIGH, CS\ is HIGH;

Other control and address bus inputs are stable; Data bus

inputs are floating

ICC2N

ICC3P

All banks open; tCK=tCK(ICC); CKE is LOW;

Other control and address inputs are stable; Data

bus inputs are floating

300

MRS[12]=0

50

125

115

-38

660

600

35

750

35

-3

Operating Current: One bank active-READ-precharge

current

ICC1

All banks idle; tCK-tCK(ICC); CKE is LOW; Other control and

address bus inputs are stable; Data bus inputs are floating

-5

ICC0

ICC2P

tCL=tCK(ICC), tRC=tRC(ICC), tRAS=tRAS MIN(ICC); CKE is

HIGH, CS\ is HIGH between valid commands; Address bus

switching, Data bus switching

IOUT=0ma; BL=4, CL=CL(ICC), AL=0; tCK = tCK(ICC), tRC-

tRC(ICC), tRAS=tRAS MIN(ICC), tRCD=tRCD(ICC); CKE is

HIGH, CS\ is HIGH between valid commands; Address bus is

switching; Data bus is switching

550

mA

650

mA

mA

mA

mA

195

All banks open, continuous burst writes; BL=4, CL=CL(ICC),

tRP=tRP(ICC); CKE is HIGH, CS\ is HIGH betwwn valid

commands; Address bus inputs are switching; Data bus

All banks open, continuous burst READS, Iout=0mA; BL=4,

CL=CL(ICC), AL=0; tCL=tCK(ICC), tRAS=tRAS MAX(ICC),

tRP=tRP(ICC); CKE is HIGH, CS\ is HIGH betwwn valid

commands; Address and Data bus inputs switching

850

700

All bank interleaving READS, IOUT = 0mA; BL=4,

CL=CL(ICC), AL=tRCD(ICC)-1xtCK(ICC); tCK=tCK(ICC),

tRC=tRC(ICC), tRRD=tRRD(ICC); CKE is HIGH, CS\ is HIGH

between valid commands; Address bus inputs are stable

during deselects; Data bus inputs are switching

tCK=tCK(ICC); refresh command at every iRFC(ICC) interval;

CKE is HIGH, CS\ is HIGH Between valid commands;

Address bus inputs are switching; Data bus inputs are

switching

600

667 MHZ

533 MHZ

400 MHZ

35

35

35

mA