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HT45F5N Datasheet(PDF) 47 Page - Holtek Semiconductor Inc |
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HT45F5N Datasheet(HTML) 47 Page - Holtek Semiconductor Inc |
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47 / 202 page  Rev. 1.00 4� �ove��e� 1�� �01� Rev. 1.00 47 �ove��e� 1�� �01� HT45F5N/HT45FH5N Power Bank ASSP Flash MCU HT45F5N/HT45FH5N Power Bank ASSP Flash MCU Bit3 LTO:LIRCSystemOSCSSTreadyflag 0:Notready 1:Ready ThisisthelowspeedsystemoscillatorSSTreadyflagwhichindicateswhenthelow speedsystemoscillatorisstableafterpoweronresetorawake-uphasoccurred.The flagwillchangetoahighlevelafter1~2cycles. Bit2 HTO:HIRCSystemOSCSSTreadyflag 0:Notready 1:Ready ThisisthehighspeedsystemoscillatorSSTreadyflagwhichindicateswhenthehigh speedsystemoscillatorisstableafterawake-uphasoccurred.Theflagwillchangeto ahighlevelafter15~16clockcyclesiftheHIRCoscillatorisused. Bit1 IDLEN:IDLEModeControl 0:Disable 1:Enable ThisistheIDLEModeControlbitanddetermineswhathappenswhentheHALT instructionisexecuted.Ifthisbitishigh,whenaHALTinstructionisexecutedthe devicewillentertheIDLEMode.IntheIDLE1ModetheCPUwillstoprunning butthesystemclockwillcontinuetokeeptheperipheralfunctionsoperational,if FSYSONbitishigh.IfFSYSONbitislow,theCPUandthesystemclockwillallstop inIDLE0mode.IfthebitislowthedevicewillentertheSLEEPModewhenaHALT instructionisexecuted. Bit0 HLCLK:SystemClockSelection 0:fH/2~fH/8orfSUB 1:fH ThisbitisusedtoselectifthefHclockorthefH/2~fH/8orfSUBclockisusedasthe systemclock.WhenthebitishighthefHclockwillbeselectedandiflowthefH/2~ fH/8orfSUBclockwillbeselected.WhensystemclockswitchesfromthefHclockto thefSUBclockandthefHclockwillbeautomaticallyswitchedofftoconservepower. CTRL Register Bit 7 6 5 4 3 2 1 0 �a�e FSYSO� — — — — LVRF LRF WRF R/W R/W — — — — R/W R/W R/W POR 0 — — — — x 0 0 "x" unknown Bit7 FSYSON:SystemClockfSYSControlinIDLEMode 0:Disable 1:Enable Bit6~3 Unimplemented,readas"0" Bit2 LVRF:LVRfunctionresetflag Describedelsewhere. Bit1 LRF:LVRCControlregistersoftwareresetflag Describedelsewhere. Bit0 WRF:WDTCControlregistersoftwareresetflag Describedelsewhere. |
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