HT45F5N datasheet(25/202 Pages) HOLTEK

25 / 202 page

Rev. 1.00

�4

�ove��e� 1�� 01�

Rev. 1.00

�5

�ove��e� 1�� 01�

HT45F5N/HT45FH5N

Power Bank ASSP Flash MCU

HT45F5N/HT45FH5N

Power Bank ASSP Flash MCU

System Architecture

Akeyfactorinthehigh-performancefeaturesoftheHoltekrangeofmicrocontrollersisattributed

totheirinternalsystemarchitecture.Thedevicetakesadvantageoftheusualfeaturesfoundwithin

RISCmicrocontrollersprovidingincreasedspeedofoperationandenhancedperformance.The

pipeliningschemeisimplementedinsuchawaythatinstructionfetchingandinstructionexecution

areoverlapped,henceinstructionsareeffectivelyexecutedinoneortwocyclesformostofthe

standardorextendedinstructionsrespectively.Theexceptionstothisarebranchorcallinstructions

whichneedonemorecycle.An8-bitwideALUisusedinpracticallyallinstructionsetoperations,

whichcarriesoutarithmeticoperations,logicoperations,rotation,increment,decrement,branch

decisions,etc.TheinternaldatapathissimplifiedbymovingdatathroughtheAccumulatorand

theALU.CertaininternalregistersareimplementedintheDataMemoryandcanbedirectly

orindirectlyaddressed.Thesimpleaddressingmethodsoftheseregistersalongwithadditional

architecturalfeaturesensurethataminimumofexternalcomponentsisrequiredtoprovidea

functionalI/OandA/Dcontrolsystemwithmaximumreliabilityandflexibility.Thismakesthe

devicesuitableforlow-cost,high-volumeproductionforcontrollerapplications.

Clocking and Pipelining

Themainsystemclock,derivedfromeithertheHIRCorLIRCoscillatorissubdividedintofour

internallygeneratednon-overlappingclocks,T1~T4.TheProgramCounterisincrementedatthe

beginningoftheT1clockduringwhichtimeanewinstructionisfetched.TheremainingT2~T4

clockscarryoutthedecodingandexecutionfunctions.Inthisway,oneT1~T4clockcycleforms

oneinstructioncycle.Althoughthefetchingandexecutionofinstructionstakesplaceinconsecutive

instructioncycles,thepipeliningstructureofthemicrocontrollerensuresthatinstructionsare

effectivelyexecutedinoneinstructioncycle.Theexceptiontothisareinstructionswherethe

contentsoftheProgramCounterarechanged,suchassubroutinecallsorjumps,inwhichcasethe

instructionwilltakeonemoreinstructioncycletoexecute.

Fetch Inst. (PC+�)

Execute Inst. (PC+1)

Oscillato� Clock

(Syste� Clock)

Phase Clock T1

Phase Clock T�

Phase Clock T3

Phase Clock T4

P�og�a� Counte�

Pipelining

PC+1

PC+�

Fetch Inst. (PC+1)

Execute Inst. (PC)

Execute Inst. (PC-1)

Fetch Inst. (PC)

System Clocking and Pipelining

HT45F5N Datasheet(PDF) 25 Page - Holtek Semiconductor Inc

HT45F5N Datasheet(HTML) 25 Page - Holtek Semiconductor Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL