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WM8960CGEFL/V Datasheet(PDF) 48 Page - Cirrus Logic |
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WM8960CGEFL/V Datasheet(HTML) 48 Page - Cirrus Logic |
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48 / 94 page ![]() WM8960 48 Rev 4.4 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R24 (18h) Additional Control (2) 6 HPSWEN 0 Headphone Switch Enable 0 = Headphone switch disabled 1 = Headphone switch enabled 5 HPSWPOL 0 Headphone Switch Polarity 0 = HPDETECT high = headphone 1 = HPDETECT high = speaker R27 (1Bh) Additional Control (3) 3 OUT3CAP 0 Capless Mode Headphone Switch Enable 0 = OUT3 unaffected by jack detect events 1 = OUT3 enabled and disabled together with HP_L and HP_R in response to jack detect events R48 (30h) Additional Control (4) 3:2 HPSEL[1:0] 00 Headphone Switch Input Select 0X = GPIO1 used for jack detect input (Requires ADCLRC pin to be configured as a GPIO) 10 = JD2 used for jack detect input 11 = JD3 used for jack detect input R23 (17h) Additional Control (1) 0 TOEN 0 Slow Clock Enable (Must be enabled for jack detect de-bounce) 0 = Slow Clock Disabled 1 = Slow Clock Enabled 1 TOCLKSEL 0 Slow Clock Selection (Used for volume update timeouts and for jack detect debounce) 0 = SYSCLK / 221 (Slower Response) 1 = SYSCLK / 219 (Faster Response) Table 30 Headphone Jack Detect L R switch opens with insertion - - LOUT1 ROUT1 LINPUT3, RINPUT3 or GPIO Headphone/ speaker switching 33k AVDD HPSWEN = 1 HPSWPOL = 0 L/ROUT1 = L/ROUT2 = 1 GPIO Figure 20 Example Headset Detection Circuit Using Normally-Open Switch L R switch closes with insertion - - LOUT1 ROUT1 LINPUT3, RINPUT3 or GPIO Headphone/ speaker switching 33k AVDD HPSWEN = 1 HPSWPOL = 1 L/ROUT1 = L/ROUT2 = 1 GPIO Figure 21 Example Headset Detection Circuit Using Normally-Closed Switch |
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