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WM8960CGEFL/V Datasheet(PDF) 85 Page - Cirrus Logic |
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WM8960CGEFL/V Datasheet(HTML) 85 Page - Cirrus Logic |
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85 / 94 page ![]() WM8960 Rev 4.4 85 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 3:0 PLLN[3:0] 1000 Integer (N) part of PLL input/output frequency ratio. Use values greater than 5 and less than 13. Clocking and Sample Rates R53 (35h) PLL (2) 8 0 Reserved 7:0 PLLK[23:16] 00110001 Fractional (K) part of PLL1 input/output frequency ratio (treat as one 24-digit binary number). Clocking and Sample Rates R54 (36h) PLL (3) 8 0 Reserved 7:0 PLLK[15:8] 00100110 Fractional (K) part of PLL1 input/output frequency ratio (treat as one 24-digit binary number). Clocking and Sample Rates R55 (37h) PLL (4) 8 0 Reserved 7:0 PLLK[7:0] 11101001 Fractional (K) part of PLL1 input/output frequency ratio (treat as one 24-digit binary number). Clocking and Sample Rates |
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